[llvm] Reapply "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321) (PR #180954)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 11 06:49:50 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-webassembly
Author: None (sstipano)
<details>
<summary>Changes</summary>
Difference from the previous version is that this one doesn't actually encode opcodes in matcher tables as 32 bits, but still as 16 bits. Hopefully since inc files don't increase, this won't cause OOM issues.
For amdgpu, this is ok because it only uses pseudo instructions for matcher tables and opcode enum is sorted so that pseudo instructions always come first.
@<!-- -->vvereschaka could you check if the issue still reproduces with this version?
---
Patch is 52.81 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/180954.diff
23 Files Affected:
- (modified) llvm/docs/HowToUseInstrMappings.rst (+2-2)
- (modified) llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h (+2-2)
- (modified) llvm/include/llvm/CodeGen/MachineInstr.h (+1-1)
- (modified) llvm/include/llvm/MC/MCInstrDesc.h (+11-11)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (+2-2)
- (modified) llvm/lib/MCA/InstrBuilder.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.h (+4-4)
- (modified) llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h (+2-2)
- (modified) llvm/lib/Target/AMDGPU/R600InstrInfo.h (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+13-13)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+82-82)
- (modified) llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp (+9-9)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+14-14)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (+6-6)
- (modified) llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp (+1-1)
- (modified) llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp (+1-1)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.h (+2-2)
- (modified) llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h (+5-3)
- (modified) llvm/test/TableGen/get-named-operand-idx.td (+5-5)
- (modified) llvm/utils/TableGen/AsmMatcherEmitter.cpp (+1-1)
- (modified) llvm/utils/TableGen/CodeGenMapTable.cpp (+5-5)
- (modified) llvm/utils/TableGen/InstrInfoEmitter.cpp (+10-10)
``````````diff
diff --git a/llvm/docs/HowToUseInstrMappings.rst b/llvm/docs/HowToUseInstrMappings.rst
index 39ae169c0c50f..17599da004ee1 100644
--- a/llvm/docs/HowToUseInstrMappings.rst
+++ b/llvm/docs/HowToUseInstrMappings.rst
@@ -61,7 +61,7 @@ Sample Example
--------------
Let's say that we want to have a function
-``int getPredOpcode(uint16_t Opcode, enum PredSense inPredSense)`` which
+``int getPredOpcode(uint32_t Opcode, enum PredSense inPredSense)`` which
takes a non-predicated instruction and returns its predicated true or false form
depending on some input flag, ``inPredSense``. The first step in the process is
to define a relationship model that relates predicated instructions to their
@@ -107,7 +107,7 @@ instruction since they are the ones used to query the interface function.
TableGen uses the above relationship model to emit relation table that maps
non-predicated instructions with their predicated forms. It also outputs the
interface function
-``int getPredOpcode(uint16_t Opcode, enum PredSense inPredSense)`` to query
+``int getPredOpcode(uint32_t Opcode, enum PredSense inPredSense)`` to query
the table. Here, Function ``getPredOpcode`` takes two arguments, opcode of the
current instruction and PredSense of the desired instruction, and returns
predicated form of the instruction, if found in the relation table.
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index 78b189d44e285..8f6586e79d78a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -1058,7 +1058,7 @@ bool GIMatchTableExecutor::executeMatchTable(
case GIR_MutateOpcode: {
uint64_t OldInsnID = readULEB();
uint64_t NewInsnID = readULEB();
- uint16_t NewOpcode = readU16();
+ uint32_t NewOpcode = readU16();
if (NewInsnID >= OutMIs.size())
OutMIs.resize(NewInsnID + 1);
@@ -1079,7 +1079,7 @@ bool GIMatchTableExecutor::executeMatchTable(
case GIR_BuildRootMI:
case GIR_BuildMI: {
uint64_t NewInsnID = (MatcherOpcode == GIR_BuildRootMI) ? 0 : readULEB();
- uint16_t Opcode = readU16();
+ uint32_t Opcode = readU16();
if (NewInsnID >= OutMIs.size())
OutMIs.resize(NewInsnID + 1);
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 29da32c931eea..90a9967b97017 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -156,7 +156,7 @@ class MachineInstr
uint8_t AsmPrinterFlags;
/// Cached opcode from MCID.
- uint16_t Opcode;
+ uint32_t Opcode;
/// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
/// defined by this instruction.
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index 69dd3e2848832..396995edc117f 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -203,17 +203,17 @@ class MCInstrDesc {
// the <Target>Insts table because they rely on knowing their own address to
// find other information elsewhere in the same table.
- unsigned short Opcode; // The opcode number
- unsigned short NumOperands; // Num of args (may be more if variable_ops)
- unsigned char NumDefs; // Num of args that are definitions
- unsigned char Size; // Number of bytes in encoding.
- unsigned short SchedClass; // enum identifying instr sched class
- unsigned char NumImplicitUses; // Num of regs implicitly used
- unsigned char NumImplicitDefs; // Num of regs implicitly defined
- unsigned short OpInfoOffset; // Offset to info about operands
- unsigned short ImplicitOffset; // Offset to start of implicit op list
- uint64_t Flags; // Flags identifying machine instr class
- uint64_t TSFlags; // Target Specific Flag values
+ uint32_t Opcode; // The opcode number.
+ uint16_t NumOperands; // Num of args (may be more if variable_ops)
+ uint8_t NumDefs; // Num of args that are definitions
+ uint8_t Size; // Number of bytes in encoding.
+ uint16_t SchedClass; // enum identifying instr sched class
+ uint8_t NumImplicitUses; // Num of regs implicitly used
+ uint8_t NumImplicitDefs; // Num of regs implicitly defined
+ uint16_t OpInfoOffset; // Offset to info about operands
+ uint16_t ImplicitOffset; // Offset to start of implicit op list
+ uint64_t Flags; // Flags identifying machine instr class
+ uint64_t TSFlags; // Target Specific Flag values
/// Returns the value of the specified operand constraint if
/// it is present. Returns -1 if it is not present.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index ab70b200d2965..3e61031c18d7b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -4227,8 +4227,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_MorphNodeTo2GlueInput:
case OPC_MorphNodeTo1GlueOutput:
case OPC_MorphNodeTo2GlueOutput: {
- uint16_t TargetOpc = MatcherTable[MatcherIndex++];
- TargetOpc |= static_cast<uint16_t>(MatcherTable[MatcherIndex++]) << 8;
+ uint32_t TargetOpc = MatcherTable[MatcherIndex++];
+ TargetOpc |= (MatcherTable[MatcherIndex++] << 8);
unsigned EmitNodeInfo;
if (Opcode >= OPC_EmitNode1None && Opcode <= OPC_EmitNode2Chain) {
if (Opcode >= OPC_EmitNode0Chain && Opcode <= OPC_EmitNode2Chain)
diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp
index ffd6a8d5c14a8..32b8cf5c38b46 100644
--- a/llvm/lib/MCA/InstrBuilder.cpp
+++ b/llvm/lib/MCA/InstrBuilder.cpp
@@ -563,7 +563,7 @@ InstrBuilder::createInstrDescImpl(const MCInst &MCI,
"Itineraries are not yet supported!");
// Obtain the instruction descriptor from the opcode.
- unsigned short Opcode = MCI.getOpcode();
+ unsigned Opcode = MCI.getOpcode();
const MCInstrDesc &MCDesc = MCII.get(Opcode);
const MCSchedModel &SM = STI.getSchedModel();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 2ccde3e661de5..ac6b9dd5dbd68 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -890,11 +890,11 @@ enum SMEMatrixType {
#undef TSFLAG_INSTR_FLAGS
#undef TSFLAG_SME_MATRIX_TYPE
-int getSVEPseudoMap(uint16_t Opcode);
-int getSVERevInstr(uint16_t Opcode);
-int getSVENonRevInstr(uint16_t Opcode);
+int64_t getSVEPseudoMap(uint32_t Opcode);
+int64_t getSVERevInstr(uint32_t Opcode);
+int64_t getSVENonRevInstr(uint32_t Opcode);
-int getSMEPseudoMap(uint16_t Opcode);
+int64_t getSMEPseudoMap(uint32_t Opcode);
}
} // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
index afaa19013bfc2..9ec12131d7236 100644
--- a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
+++ b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
@@ -322,13 +322,13 @@ bool AMDGPUCustomBehaviour::hasModifiersSet(
}
// taken from SIInstrInfo::isGWS()
-bool AMDGPUCustomBehaviour::isGWS(uint16_t Opcode) const {
+bool AMDGPUCustomBehaviour::isGWS(uint32_t Opcode) const {
const MCInstrDesc &MCID = MCII.get(Opcode);
return MCID.TSFlags & SIInstrFlags::GWS;
}
// taken from SIInstrInfo::isAlwaysGDS()
-bool AMDGPUCustomBehaviour::isAlwaysGDS(uint16_t Opcode) const {
+bool AMDGPUCustomBehaviour::isAlwaysGDS(uint32_t Opcode) const {
return Opcode == AMDGPU::DS_ORDERED_COUNT ||
Opcode == AMDGPU::DS_ADD_GS_REG_RTN ||
Opcode == AMDGPU::DS_SUB_GS_REG_RTN || isGWS(Opcode);
diff --git a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
index 4d0c163c5ea74..aeb5c032daee4 100644
--- a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
+++ b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
@@ -68,9 +68,9 @@ class AMDGPUCustomBehaviour : public CustomBehaviour {
bool hasModifiersSet(const std::unique_ptr<Instruction> &Inst,
AMDGPU::OpName OpName) const;
/// Helper function used in generateWaitCntInfo()
- bool isGWS(uint16_t Opcode) const;
+ bool isGWS(uint32_t Opcode) const;
/// Helper function used in generateWaitCntInfo()
- bool isAlwaysGDS(uint16_t Opcode) const;
+ bool isAlwaysGDS(uint32_t Opcode) const;
/// Helper function used in generateWaitCntInfo()
bool isVMEM(const MCInstrDesc &MCID);
/// This method gets called from checkCustomHazard when mca is attempting to
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
index 68bbac103cb9a..b96c17e137072 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
@@ -326,7 +326,7 @@ class R600InstrInfo final : public R600GenInstrInfo {
namespace R600 {
-int getLDSNoRetOp(uint16_t Opcode);
+int64_t getLDSNoRetOp(uint32_t Opcode);
} //End namespace AMDGPU
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 996c92a8b5078..24aa31a318df3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1159,7 +1159,7 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
- int NewOpc;
+ int64_t NewOpc;
// Try to map original to commuted opcode
NewOpc = AMDGPU::getCommuteRev(Opcode);
@@ -4513,7 +4513,7 @@ bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
changesVGPRIndexingMode(MI);
}
-bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
+bool SIInstrInfo::isAlwaysGDS(uint32_t Opcode) const {
return Opcode == AMDGPU::DS_ORDERED_COUNT ||
Opcode == AMDGPU::DS_ADD_GS_REG_RTN ||
Opcode == AMDGPU::DS_SUB_GS_REG_RTN || isGWS(Opcode);
@@ -5141,7 +5141,7 @@ bool SIInstrInfo::verifyCopy(const MachineInstr &MI,
bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const {
- uint16_t Opcode = MI.getOpcode();
+ uint32_t Opcode = MI.getOpcode();
const MachineFunction *MF = MI.getMF();
const MachineRegisterInfo &MRI = MF->getRegInfo();
@@ -5398,7 +5398,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
}
- uint16_t BasicOpcode = AMDGPU::getBasicFromSDWAOp(Opcode);
+ uint32_t BasicOpcode = AMDGPU::getBasicFromSDWAOp(Opcode);
if (isVOPC(BasicOpcode)) {
if (!ST.hasSDWASdst() && DstIdx != -1) {
// Only vcc allowed as dst on VI for VOPC
@@ -9956,7 +9956,7 @@ unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register SrcReg,
}
bool SIInstrInfo::canAddToBBProlog(const MachineInstr &MI) const {
- uint16_t Opcode = MI.getOpcode();
+ uint32_t Opcode = MI.getOpcode();
// Check if it is SGPR spill or wwm-register spill Opcode.
if (isSGPRSpill(Opcode) || isWWMRegSpillOpcode(Opcode))
return true;
@@ -10357,9 +10357,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
Opcode = MFMAOp;
}
- int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
+ int64_t MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
- if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts())
+ if (MCOp == (uint32_t)-1 && ST.hasGFX1250Insts())
MCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX12);
// -1 means that Opcode is already a native instruction.
@@ -10367,20 +10367,20 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
return Opcode;
if (ST.hasGFX90AInsts()) {
- uint16_t NMCOp = (uint16_t)-1;
+ uint32_t NMCOp = (uint32_t)-1;
if (ST.hasGFX940Insts())
NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX940);
- if (NMCOp == (uint16_t)-1)
+ if (NMCOp == (uint32_t)-1)
NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX90A);
- if (NMCOp == (uint16_t)-1)
+ if (NMCOp == (uint32_t)-1)
NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX9);
- if (NMCOp != (uint16_t)-1)
+ if (NMCOp != (uint32_t)-1)
MCOp = NMCOp;
}
- // (uint16_t)-1 means that Opcode is a pseudo instruction that has
+ // (uint32_t)-1 means that Opcode is a pseudo instruction that has
// no encoding in the given subtarget generation.
- if (MCOp == (uint16_t)-1)
+ if (MCOp == (uint32_t)-1)
return -1;
if (isAsmOnlyOpcode(MCOp))
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 85585cbfc628a..0b54513bb6114 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -466,7 +466,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SALU;
}
- bool isSALU(uint16_t Opcode) const {
+ bool isSALU(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SALU;
}
@@ -474,7 +474,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VALU;
}
- bool isVALU(uint16_t Opcode) const {
+ bool isVALU(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VALU;
}
@@ -482,7 +482,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI);
}
- bool isImage(uint16_t Opcode) const {
+ bool isImage(uint32_t Opcode) const {
return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode);
}
@@ -490,7 +490,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return isMUBUF(MI) || isMTBUF(MI) || isImage(MI) || isFLAT(MI);
}
- bool isVMEM(uint16_t Opcode) const {
+ bool isVMEM(uint32_t Opcode) const {
return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode);
}
@@ -498,7 +498,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
}
- bool isSOP1(uint16_t Opcode) const {
+ bool isSOP1(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOP1;
}
@@ -506,7 +506,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
}
- bool isSOP2(uint16_t Opcode) const {
+ bool isSOP2(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOP2;
}
@@ -514,7 +514,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
}
- bool isSOPC(uint16_t Opcode) const {
+ bool isSOPC(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOPC;
}
@@ -522,7 +522,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
}
- bool isSOPK(uint16_t Opcode) const {
+ bool isSOPK(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOPK;
}
@@ -530,7 +530,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
}
- bool isSOPP(uint16_t Opcode) const {
+ bool isSOPP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOPP;
}
@@ -538,7 +538,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
}
- bool isPacked(uint16_t Opcode) const {
+ bool isPacked(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
}
@@ -546,7 +546,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
}
- bool isVOP1(uint16_t Opcode) const {
+ bool isVOP1(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOP1;
}
@@ -554,7 +554,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
}
- bool isVOP2(uint16_t Opcode) const {
+ bool isVOP2(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOP2;
}
@@ -564,13 +564,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isVOP3(const MachineInstr &MI) { return isVOP3(MI.getDesc()); }
- bool isVOP3(uint16_t Opcode) const { return isVOP3(get(Opcode)); }
+ bool isVOP3(uint32_t Opcode) const { return isVOP3(get(Opcode)); }
static bool isSDWA(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
}
- bool isSDWA(uint16_t Opcode) const {
+ bool isSDWA(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SDWA;
}
@@ -578,7 +578,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
}
- bool isVOPC(uint16_t Opcode) const {
+ bool isVOPC(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOPC;
}
@@ -586,7 +586,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
}
- bool isMUBUF(uint16_t Opcode) const {
+ bool isMUBUF(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
}
@@ -594,7 +594,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
}
- bool isMTBUF(uint16_t Opcode) const {
+ bool isMTBUF(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
}
@@ -606,7 +606,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
}
- bool isSMRD(uint16_t Opcode) const {
+ bool isSMRD(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SMRD;
}
@@ -616,7 +616,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::DS;
}
- bool isDS(uint16_t Opcode) const {
+ bool isDS(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::DS;
}
@@ -625,7 +625,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
(MI.getDesc().TSFlags & SIInstrFlags::TENSOR_CNT);
}
- bool isLDSDMA(uint16_t Opcode) {
+ bool isLDSDMA(uint32_t Opcode) {
return (isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode))) ||
(get(Opcode).TSFlags & SIInstrFlags::TENSOR_CNT);
}
@@ -634,17 +634,17 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::GWS;
}
- bool isGWS(uint16_t Opcode) const {
+ bool isGWS(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::GWS;
}
- bool isAlwaysGDS(uint16_t Opcode) const;
+ bool isAlwaysGDS(uint32_t Opcode) const;
static bool isMIMG(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
}
- bool isMIMG(uint16_t Opcode) const {
+ bool isMIMG(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::MIMG;
}
@@ -652,7 +652,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VIMAGE;
}
- bool isVIMAGE(uint16_t Opcode) const {
+ bool isVIMAGE(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VIMAGE;
}
@@ -660,7 +660,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VSAMPLE;
}
- bool isVSAMPLE(uint16_t Opcode) const {
+ bool isVSAMPLE(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VSAMPLE;
}
@@ -668,7 +668,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
}
- bool isGather4(uint16_t Opcode) const {
+ bool isGather4(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::Gather4;
}
@@ -683,7 +683,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
}
- bool isSegmentSpecificFLAT(uint16_t Opcode) const {
+ bool isSegmentSpecificFLAT(uint32_t Opcode) const {
auto Flags = get(Opcode).TSFlags;
return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
}
@@ -692,7 +692,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/180954
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