[llvm] [AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (PR #180940)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 11 05:24:59 PST 2026
https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/180940
This matches the hardware behavior.
>From edfc30fb3255c782b60c05a09a3969713b9ca55f Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 11 Feb 2026 13:22:48 +0000
Subject: [PATCH] [AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU
insertion
This matches the hardware behavior.
---
.../Target/AMDGPU/AMDGPUInsertDelayAlu.cpp | 4 +++-
.../CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll | 12 +++++------
.../GlobalISel/llvm.amdgcn.rsq.clamp.ll | 12 ++++-------
llvm/test/CodeGen/AMDGPU/frem.ll | 20 +++++++++----------
llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir | 17 ++++++++++++++++
5 files changed, 40 insertions(+), 25 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
index 7c84edf2a60bc..d1b9fb4115f66 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
@@ -68,7 +68,9 @@ class AMDGPUInsertDelayAlu {
// Get the delay type for a MachineInstr.
DelayType getDelayType(const MachineInstr &MI) {
- if (SIInstrInfo::isTRANS(MI))
+ // Non-F64 TRANS instructions use a separate delay type.
+ if (SIInstrInfo::isTRANS(MI) &&
+ !AMDGPU::isDPMACCInstruction(MI.getOpcode()))
return TRANS;
// WMMA XDL ops are treated the same as TRANS.
if (ST->hasGFX1250Insts() && SII->isXDLWMMA(MI))
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
index 31fc1ee538957..3f6a6ac44f543 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
@@ -832,7 +832,7 @@ define <2 x double> @v_fdiv_v2f64(<2 x double> %a, <2 x double> %b) {
; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[0:1]
; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3]
; GFX11-NEXT: v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -1065,7 +1065,7 @@ define <2 x double> @v_fdiv_v2f64_ulp25(<2 x double> %a, <2 x double> %b) {
; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[0:1]
; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3]
; GFX11-NEXT: v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -1225,7 +1225,7 @@ define <2 x double> @v_rcp_v2f64(<2 x double> %x) {
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], 1.0
; GFX11-NEXT: v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[0:1], 1.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -1385,7 +1385,7 @@ define <2 x double> @v_rcp_v2f64_arcp(<2 x double> %x) {
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], 1.0
; GFX11-NEXT: v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[0:1], 1.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -1612,7 +1612,7 @@ define <2 x double> @v_rcp_v2f64_ulp25(<2 x double> %x) {
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], 1.0
; GFX11-NEXT: v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[0:1], 1.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -1845,7 +1845,7 @@ define <2 x double> @v_fdiv_v2f64_arcp_ulp25(<2 x double> %a, <2 x double> %b) {
; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[0:1]
; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3]
; GFX11-NEXT: v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
index 26cdbb11d27d6..4a6e24b700663 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
@@ -95,11 +95,10 @@ define double @v_rsq_clamp_f64(double %src) #0 {
; GFX12-NEXT: v_rsq_f64_e32 v[0:1], v[0:1]
; GFX12-NEXT: v_mov_b32_e32 v2, -1
; GFX12-NEXT: v_mov_b32_e32 v3, 0x7fefffff
-; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: v_mov_b32_e32 v2, -1
; GFX12-NEXT: v_mov_b32_e32 v3, 0xffefffff
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src)
@@ -135,11 +134,10 @@ define double @v_rsq_clamp_fabs_f64(double %src) #0 {
; GFX12-NEXT: v_rsq_f64_e64 v[0:1], |v[0:1]|
; GFX12-NEXT: v_mov_b32_e32 v2, -1
; GFX12-NEXT: v_mov_b32_e32 v3, 0x7fefffff
-; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: v_mov_b32_e32 v2, -1
; GFX12-NEXT: v_mov_b32_e32 v3, 0xffefffff
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call double @llvm.fabs.f64(double %src)
@@ -208,11 +206,10 @@ define double @v_rsq_clamp_undef_f64() #0 {
; GFX12-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
; GFX12-NEXT: v_mov_b32_e32 v2, -1
; GFX12-NEXT: v_mov_b32_e32 v3, 0x7fefffff
-; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: v_mov_b32_e32 v2, -1
; GFX12-NEXT: v_mov_b32_e32 v3, 0xffefffff
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double poison)
@@ -279,11 +276,10 @@ define double @v_rsq_clamp_f64_non_ieee(double %src) #2 {
; GFX12-NEXT: v_rsq_f64_e32 v[0:1], v[0:1]
; GFX12-NEXT: v_mov_b32_e32 v2, -1
; GFX12-NEXT: v_mov_b32_e32 v3, 0x7fefffff
-; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: v_mov_b32_e32 v2, -1
; GFX12-NEXT: v_mov_b32_e32 v3, 0xffefffff
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src)
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 5d243189d516a..bf153a88982e0 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -4224,7 +4224,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
; GFX1150-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX1150-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX1150-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4330,7 +4330,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
; GFX1200-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX1200-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX1200-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4622,7 +4622,7 @@ define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1150-NEXT: global_load_b64 v[2:3], v12, s[4:5]
; GFX1150-NEXT: s_waitcnt vmcnt(0)
; GFX1150-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; GFX1150-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4655,7 +4655,7 @@ define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1200-NEXT: global_load_b64 v[2:3], v12, s[4:5]
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; GFX1200-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4900,7 +4900,7 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
; GFX1150-NEXT: global_load_b64 v[2:3], v12, s[4:5]
; GFX1150-NEXT: s_waitcnt vmcnt(0)
; GFX1150-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; GFX1150-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4933,7 +4933,7 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
; GFX1200-NEXT: global_load_b64 v[2:3], v12, s[4:5]
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; GFX1200-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17172,7 +17172,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
; GFX1150-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
-; GFX1150-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX1150-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17259,7 +17259,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
; GFX1150-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
-; GFX1150-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX1150-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17371,7 +17371,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
; GFX1200-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
-; GFX1200-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX1200-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17462,7 +17462,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
; GFX1200-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
-; GFX1200-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX1200-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir b/llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir
index c287fb3614496..3addab3508140 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir
+++ b/llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir
@@ -379,6 +379,15 @@
; CHECK-NEXT: v_mul_f32_e64 v0, v0, v0
ret void;
}
+
+ define void @trans64() {
+ ; CHECK-LABEL: trans64:
+ ; CHECK: ; %bb.0:
+ ; CHECK-NEXT: v_rcp_f64_e32 v[0:1], v[0:1]
+ ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+ ; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], v[0:1]
+ ret void;
+ }
...
---
@@ -762,3 +771,11 @@ body: |
$vgpr0 = V_MUL_F32_e64 0, $vgpr0, 0, $vgpr0, 0, 0, implicit $mode, implicit $exec
...
+# Check that F64 TRANS instructions are treated as VALU.
+---
+name: trans64
+body: |
+ bb.0:
+ $vgpr0_vgpr1 = V_RCP_F64_e32 $vgpr0_vgpr1, implicit $exec, implicit $mode
+ $vgpr0_vgpr1 = V_ADD_F64_e64 0, $vgpr0_vgpr1, 0, $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $mode
+...
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