[llvm] [AMDGPU] Allow hoisting of V_READFIRSTLANE_B32 for uniform operand (PR #178312)

[Jay Foad via llvm-commits]

jayfoad wrote:

> > > Now you have to imagine a MIR transformation pass that replaces all uses of %3 with %4 in bb.1.body.
> > 
> > 
> > I think this is still correct: inside the `body` it is correct because both values equal and value is the same. Past the `body` in the `UnifiedReturnBlock` values may diverge and that is represented by the divergent `PHI`, so we are back to the correct value for any use.
> 
> I don't understand. The example talks about hoisting the noconvergent readfirstlane from inside the loop to _above_ the loop into `bb.0.entry`, not past the body down into `bb.2.UnifiedReturnBlock`.

Right. I have edited the comment to try to make this even clearer, by showing the full MIR after the hoisting.

https://github.com/llvm/llvm-project/pull/178312