[llvm] [AArch64][ISel] Add clmul to pmullb/t lowering (PR #180568)

[Matthew Devereau via llvm-commits]

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@@ -2015,6 +2015,9 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
   }
 
+  if (Subtarget->hasSVE2AES())
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MDevereau wrote:

Ok, I see how it was incorrect. It's quite confusing when writing these patterns as instructions like 

https://developer.arm.com/documentation/111108/2025-12/SVE-Instructions/AESE--vectors---AES-single-round-encryption-?lang=en

are described as being SVE2 in the documentation and made with tablegen multiclasses called sve2... when the instruction does not seem to actually require sve2 predicates

https://github.com/llvm/llvm-project/pull/180568