[llvm] [AMDGPU][Scheduler] Fix inconsistent MI slots after rematerialization revert (PR #180646)

[Lucas Ramirez via llvm-commits]

================
@@ -3109,30 +3085,66 @@ void PreRARematStage::finalizeGCNSchedStage() {
     commitRematerializations();
     return;
   }
+
+  // It is possible that re-scheduling lowers occupancy over the one achieved
+  // just through rematerializations, in which case we revert re-scheduling in
+  // all regions but do not roll back rematerializations.
+  const bool ShouldRollbackRemats = AchievedOcc < *TargetOcc;
+
+  // When we both need to revert re-scheduling and rollback rematerializations,
----------------
lucas-rami wrote:

They will still be DBG_VALUE during the revert but they will get properly deleted after by `commitRematerializations` in that case. Slots will be stale "in flight" but when `finalizeGCNSchedStage` terminates MI/slot order will be coherent.

https://github.com/llvm/llvm-project/pull/180646