[llvm] [AArch64]Add SCR2_EL3 system register (PR #180918)

[via llvm-commits]

https://github.com/CarolineConcatto created https://github.com/llvm/llvm-project/pull/180918

The link to the system register:

https://developer.arm.com/documentation/111107/2025-12/AArch64-Registers/SCR2-EL3--Secure-Configuration-Register?lang=en

>From a593e1e68d4ea5fc1b4385e340ea46a4d9f7367a Mon Sep 17 00:00:00 2001
From: CarolineConcatto <caroline.concatto at arm.com>
Date: Wed, 11 Feb 2026 11:14:39 +0000
Subject: [PATCH] [AArch64]Add SCR2_EL3 system register

The link to the system register:

https://developer.arm.com/documentation/111107/2025-12/AArch64-Registers/SCR2-EL3--Secure-Configuration-Register?lang=en
---
 .../Target/AArch64/AArch64SystemOperands.td   |  4 ++++
 llvm/test/MC/AArch64/armv9.7-scr2.s           | 24 +++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 llvm/test/MC/AArch64/armv9.7-scr2.s

diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index a1ab0da7b051c..d91edf7a7b89d 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -2372,6 +2372,10 @@ def : RWSysReg<"MPAMVIDCR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b000>;
 def : RWSysReg<"MPAMVIDSR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b001>;
 def : RWSysReg<"MPAMVIDSR_EL3", 0b11, 0b110, 0b1010, 0b0111, 0b001>;
 
+// v9.7a General Improvements
+//                                        Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"SCR2_EL3",                0b11, 0b110, 0b0001, 0b0010, 0b010>;
+
 //===----------------------------------------------------------------------===//
 // FEAT_SRMASK v9.6a registers
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AArch64/armv9.7-scr2.s b/llvm/test/MC/AArch64/armv9.7-scr2.s
new file mode 100644
index 0000000000000..fb3a8e5d14eff
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.7-scr2.s
@@ -0,0 +1,24 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \
+// RUN:        | llvm-objdump -d  - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding  < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64  -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING
+
+//------------------------------------------------------------------------------
+// Armv9.7-A FEAT_SCR2_EL3
+//------------------------------------------------------------------------------
+
+mrs x0, SCR2_EL3
+// CHECK-INST:  mrs x0, SCR2_EL3
+// CHECK-ENCODING: [0x40,0x12,0x3e,0xd5]
+// CHECK-UNKNOWN: d53e1240
+
+msr SCR2_EL3, x0
+// CHECK-INST: msr SCR2_EL3, x0
+// CHECK-ENCODING: [0x40,0x12,0x1e,0xd5]
+// CHECK-UNKNOWN: d51e1240