[lldb] [llvm] [lldb][Process/FreeBSDKernel] Add riscv64 support (PR #180670)

[David Spickett via llvm-commits]

================
@@ -0,0 +1,110 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file contains the definition of the
+/// RegisterContextFreeBSDKernel_riscv64 class, which is used for reading
+/// registers from PCB on riscv64 kernel dump.
+///
+//===----------------------------------------------------------------------===//
+
+#include "RegisterContextFreeBSDKernel_riscv64.h"
+
+#include "lldb/Target/Process.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "llvm/Support/Endian.h"
+
+using namespace lldb;
+using namespace lldb_private;
+
+RegisterContextFreeBSDKernel_riscv64::RegisterContextFreeBSDKernel_riscv64(
+    Thread &thread, std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up,
+    lldb::addr_t pcb_addr)
+    : RegisterContextPOSIX_riscv64(thread, std::move(register_info_up)),
+      m_pcb_addr(pcb_addr) {}
+
+bool RegisterContextFreeBSDKernel_riscv64::ReadGPR() { return true; }
+
+bool RegisterContextFreeBSDKernel_riscv64::ReadFPR() { return true; }
+
+bool RegisterContextFreeBSDKernel_riscv64::WriteGPR() {
+  assert(0);
+  return false;
+}
+
+bool RegisterContextFreeBSDKernel_riscv64::WriteFPR() {
+  assert(0);
+  return false;
+}
+
+bool RegisterContextFreeBSDKernel_riscv64::ReadRegister(
+    const RegisterInfo *reg_info, RegisterValue &value) {
+  if (m_pcb_addr == LLDB_INVALID_ADDRESS)
+    return false;
+
+  // https://cgit.freebsd.org/src/tree/sys/riscv/include/pcb.h
+  struct {
+    llvm::support::ulittle64_t ra;
+    llvm::support::ulittle64_t sp;
+    llvm::support::ulittle64_t gp;
+    llvm::support::ulittle64_t tp;
+    llvm::support::ulittle64_t s[12];
+  } pcb;
+
+  Status error;
+  size_t rd =
+      m_thread.GetProcess()->ReadMemory(m_pcb_addr, &pcb, sizeof(pcb), error);
+  if (rd != sizeof(pcb))
+    return false;
+
+  uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+  switch (reg) {
+  case gpr_pc_riscv:
+  // Supply the RA as PC as well to simulate the PC as if the thread had just
+  // returned.
----------------
DavidSpickett wrote:

Put this comment above so that we have:
```
case A:
case B:
  break;
```
A bit easier to see at a glance that it's intentional fall through.

https://github.com/llvm/llvm-project/pull/180670