[llvm] c3b6f14 - [RISCV] Remove explicitly adding spilled registers as liveins. (#180483)

[via llvm-commits]

Author: Jim Lin
Date: 2026-02-11T17:16:38+08:00
New Revision: c3b6f14a89f518288dfdafbf711827c9ffb4adc5

URL: https://github.com/llvm/llvm-project/commit/c3b6f14a89f518288dfdafbf711827c9ffb4adc5
DIFF: https://github.com/llvm/llvm-project/commit/c3b6f14a89f518288dfdafbf711827c9ffb4adc5.diff

LOG: [RISCV] Remove explicitly adding spilled registers as liveins. (#180483)

We didn't explicitly add spilled registers as liveins for CM_PUSH as
well. The liveins of the basic block will be updated by updateLiveness
in PrologEpilogInserter.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 24b83026bf824..7212ed39eb70e 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -2153,12 +2153,9 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
             .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
             .setMIFlag(MachineInstr::FrameSetup);
 
-    for (auto &CS : CSI) {
-      // Add registers spilled as implicit used.
+    // Add registers spilled as implicit used.
+    for (auto &CS : CSI)
       NewMI.addUse(CS.getReg(), RegState::Implicit);
-      // Add registers spilled in libcall as liveins.
-      MBB.addLiveIn(CS.getReg());
-    }
   }
 
   // Manually spill values not spilled by libcall & Push/Pop.