[llvm] 1094775 - [X86] Fix lower1BitShuffle blend-with-zero shuffles to AND mask (#180472)

[via llvm-commits]

Author: woruyu
Date: 2026-02-11T09:49:29+08:00
New Revision: 1094775692bf6d44358629ded7c4d779785b2d3e

URL: https://github.com/llvm/llvm-project/commit/1094775692bf6d44358629ded7c4d779785b2d3e
DIFF: https://github.com/llvm/llvm-project/commit/1094775692bf6d44358629ded7c4d779785b2d3e.diff

LOG: [X86] Fix lower1BitShuffle blend-with-zero shuffles to AND mask (#180472)

### Summary
This PR resolves https://github.com/llvm/llvm-project/issues/180426.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/avx512bwvl-arith.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index b8357087d30b1..9c6cc95cc5eac 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18367,9 +18367,17 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
     return Zeroable[M.index()] || (M.value() == (int)M.index());
   });
   if (IsBlendWithZero) {
-    EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumElts);
-    SDValue BlendMask = DAG.getConstant(~Zeroable, DL, IntVT);
-    return DAG.getNode(ISD::AND, DL, VT, V1, DAG.getBitcast(VT, BlendMask));
+    const unsigned Width = std::max<unsigned>(NumElts, 8u);
+    MVT IntVT = MVT::getIntegerVT(Width);
+
+    APInt MaskValue = (~Zeroable).zextOrTrunc(Width);
+    SDValue MaskNode = DAG.getConstant(MaskValue, DL, IntVT);
+
+    MVT MaskVecVT = MVT::getVectorVT(MVT::i1, Width);
+    SDValue MaskVecNode = DAG.getBitcast(MaskVecVT, MaskNode);
+
+    SDValue MaskVec = DAG.getExtractSubvector(DL, VT, MaskVecNode, 0);
+    return DAG.getNode(ISD::AND, DL, VT, V1, MaskVec);
   }
 
   MVT ExtVT;

diff  --git a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
index decab7b485c4d..a7b93924e6f82 100644
--- a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
@@ -250,3 +250,17 @@ define i16 @PR90356(<16 x i1> %a) {
   %2 = bitcast <16 x i1> %1 to i16
   ret i16 %2
 }
+
+define <4 x i1> @PR180472(<4 x i1> %0) {
+; CHECK-LABEL: PR180472:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpslld $31, %xmm0, %xmm0
+; CHECK-NEXT:    movb $5, %al
+; CHECK-NEXT:    kmovd %eax, %k1
+; CHECK-NEXT:    vptestmd %xmm0, %xmm0, %k1 {%k1}
+; CHECK-NEXT:    vpcmpeqd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vmovdqa32 %xmm0, %xmm0 {%k1} {z}
+; CHECK-NEXT:    retq
+  %x = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+  ret <4 x i1> %x
+}