[llvm] [MIRParser] Accept sub-register for implicit operand verification (PR #180707)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> Could/should we use a different variant for the w32 v. w64 instructions? I see that we do that in some places, but I don't think it's consistent.

Yes. RegClassByHwMode solved the problem for virtual register operands. For physical registers, the current option is to duplicate the instructions for wave32 and wave64 variants. There's kind of annoying number of them though


https://github.com/llvm/llvm-project/pull/180707