[llvm] [RISCV] Refactor the MC layer SiFive VCIX classes. (PR #180433)

[Craig Topper via llvm-commits]

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@@ -17,14 +17,37 @@
 def VCIXVS2    : RISCVVConstraint<VS2 = 1>;
 def VCIXVS2VS1 : RISCVVConstraint<VS2 = 1, VS1 = 1>;
 
-class VCIXType<bits<4> val> {
+class VCIXType<bits<4> val, string suffix> {
   bits<4> Val = val;
-}
-
-def VCIX_X   : VCIXType<0b0000>;
-def VCIX_XV  : VCIXType<0b0010>;
-def VCIX_XVV : VCIXType<0b1010>;
-def VCIX_XVW : VCIXType<0b1111>;
+  string Suffix = suffix;
+  bit Vs2IsImmediate = 0;   // Whether vs2 is an immediate
+  bit VdIsSource = 0;       // Whether vd appears in ins as a source operand
+  bit IsWidening = 0;       // Whether this is a widening instruction (XVW)
+}
+
+def VCIX_X   : VCIXType<0b0000, "">   { let Vs2IsImmediate = 1; }
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topperc wrote:

I've replaced it with `Rs1` instead.

https://github.com/llvm/llvm-project/pull/180433