[llvm] [AMDGPU][SIInsertWaitcnts][NFC] Drop `using llvm::AMDGPU` (PR #180782)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 94c0883db..2eb9a7bfe 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -241,7 +241,7 @@ static bool updateVMCntOnly(const MachineInstr &Inst) {
 }
 
 #ifndef NDEBUG
-  static bool isNormalMode(AMDGPU::InstCounterType MaxCounter) {
+static bool isNormalMode(AMDGPU::InstCounterType MaxCounter) {
   return MaxCounter == AMDGPU::NUM_NORMAL_INST_CNTS;
 }
 #endif // NDEBUG
@@ -901,7 +901,8 @@ private:
     if (T != AMDGPU::EXP_CNT)
       return;
 
-    if (getScoreRange(AMDGPU::EXP_CNT) > getWaitCountMax(Context->getLimits(), AMDGPU::EXP_CNT))
+    if (getScoreRange(AMDGPU::EXP_CNT) >
+        getWaitCountMax(Context->getLimits(), AMDGPU::EXP_CNT))
       ScoreLBs[AMDGPU::EXP_CNT] =
           ScoreUBs[AMDGPU::EXP_CNT] -
           getWaitCountMax(Context->getLimits(), AMDGPU::EXP_CNT);
@@ -1164,7 +1165,8 @@ void WaitcntBrackets::updateByEvent(WaitEventType E, MachineInstr &Inst) {
     // Special cases where implicit register defs exists, such as M0 or VCC,
     // but none with memory instructions.
     for (const MachineOperand &Op : Inst.defs()) {
-      if (T == AMDGPU::LOAD_CNT || T == AMDGPU::SAMPLE_CNT || T == AMDGPU::BVH_CNT) {
+      if (T == AMDGPU::LOAD_CNT || T == AMDGPU::SAMPLE_CNT ||
+          T == AMDGPU::BVH_CNT) {
         if (!TRI->isVectorRegister(*MRI, Op.getReg())) // TODO: add wrapper
           continue;
         if (updateVMCntOnly(Inst)) {
@@ -1379,7 +1381,8 @@ void WaitcntBrackets::simplifyXcnt(const AMDGPU::Waitcnt &CheckWait,
   // stores. VMEM loads retun in order, so if we only have loads XCnt is
   // decremented to the same number as LOADCnt.
   if (CheckWait.LoadCnt != ~0u && hasPendingEvent(VMEM_GROUP) &&
-      !hasPendingEvent(AMDGPU::STORE_CNT) && CheckWait.XCnt >= CheckWait.LoadCnt)
+      !hasPendingEvent(AMDGPU::STORE_CNT) &&
+      CheckWait.XCnt >= CheckWait.LoadCnt)
     UpdateWait.XCnt = ~0u;
   simplifyWaitcnt(AMDGPU::X_CNT, UpdateWait.XCnt);
 }
@@ -1656,7 +1659,8 @@ bool WaitcntGeneratorPreGFX12::applyPreexistingWaitcnt(
       assert(ST.hasVMemToLDSLoad());
       LLVM_DEBUG(dbgs() << "Processing S_WAITCNT_lds_direct: " << II
                         << "Before: " << Wait << '\n';);
-      ScoreBrackets.determineWaitForLDSDMA(AMDGPU::LOAD_CNT, LDSDMA_BEGIN, Wait);
+      ScoreBrackets.determineWaitForLDSDMA(AMDGPU::LOAD_CNT, LDSDMA_BEGIN,
+                                           Wait);
       LLVM_DEBUG(dbgs() << "After: " << Wait << '\n';);
 
       // It is possible (but unlikely) that this is the only wait instruction,
@@ -2391,7 +2395,8 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(
               if ((I + 1) >= NUM_LDSDMA) {
                 // We didn't have enough slot to track this LDS DMA store, it
                 // has been tracked using the common RegNo (FIRST_LDS_VGPR).
-                ScoreBrackets.determineWaitForLDSDMA(AMDGPU::LOAD_CNT, TID, Wait);
+                ScoreBrackets.determineWaitForLDSDMA(AMDGPU::LOAD_CNT, TID,
+                                                     Wait);
                 break;
               }
 

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</details>


https://github.com/llvm/llvm-project/pull/180782