[llvm] [SelectionDAG] Make sure demanded lanes for AND/MUL-by-zero are frozen (PR #180727)

[Björn Pettersson via llvm-commits]

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@@ -24273,8 +24273,17 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
           // Build the mask and return the corresponding DAG node.
           auto BuildMaskAndNode = [&](SDValue TrueVal, SDValue FalseVal,
                                       unsigned MaskOpcode) {
-            for (unsigned I = 0; I != NumElts; ++I)
+            APInt InsertedEltMask = APInt::getZero(NumElts);
+            for (unsigned I = 0; I != NumElts; ++I) {
               Mask[I] = Ops[I] ? TrueVal : FalseVal;
+              if (Ops[I])
+                InsertedEltMask.setBit(I);
+            }
+            // Make sure to freeze the source vector in case any of the elements
+            // overwritten by the insert may be poison. Otherwise those elements
+            // could end up being poison instead of 0/-1 after the AND/OR.
+            CurVec =
+                DAG.getFreeze(CurVec, InsertedEltMask, /*PoisonOnly=*/true);
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bjope wrote:

Avoided lit test diffs in one AArch64 test case by doing it this way. Haven't checked any other code base than the lit tests, so no idea really if it makes a big difference in the "real world beyond lit tests".

Relying on later SimplifyDemandedVectorElts would involve that the user of the AND/MUL for example isn't a target-specific ISD node that isn't handled well by SimplifyDemandedVectorEltsForTargetNode etc. Doing it like this makes sure that we do not make the vector more poisonous (while we allow poison in lanes that were poison already before the optimization). It is hard to tell which lanes that were guaranteed not to be poison given by the INSERT_VECTOR_ELT ops after having changed into an AND/OR, so I thought it was good to do this before "losing that information".

https://github.com/llvm/llvm-project/pull/180727