[llvm] 067f1c9 - [LoopVectorizer] Generate test checks (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 10 08:02:02 PST 2026
Author: Nikita Popov
Date: 2026-02-10T17:01:49+01:00
New Revision: 067f1c95a4520e84216ac66699b6c65bb4b47cd2
URL: https://github.com/llvm/llvm-project/commit/067f1c95a4520e84216ac66699b6c65bb4b47cd2
DIFF: https://github.com/llvm/llvm-project/commit/067f1c95a4520e84216ac66699b6c65bb4b47cd2.diff
LOG: [LoopVectorizer] Generate test checks (NFC)
Added:
Modified:
llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll
index 41d9fe0407ef3..48a9bdc12a104 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -mcpu=pwr7 -mattr=+vsx -passes=loop-vectorize,instcombine -S | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@@ -8,6 +9,94 @@ target triple = "powerpc64-unknown-linux-gnu"
@ntimes = external hidden unnamed_addr global i32, align 4
define signext i32 @s173() #0 {
+; CHECK-LABEL: define signext i32 @s173(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @ntimes, align 4
+; CHECK-NEXT: [[CMP21:%.*]] = icmp sgt i32 [[TMP0]], 0
+; CHECK-NEXT: br i1 [[CMP21]], label %[[FOR_COND1_PREHEADER_PREHEADER:.*]], label %[[FOR_END12:.*]]
+; CHECK: [[FOR_COND1_PREHEADER_PREHEADER]]:
+; CHECK-NEXT: br label %[[FOR_COND1_PREHEADER:.*]]
+; CHECK: [[FOR_COND1_PREHEADER]]:
+; CHECK-NEXT: [[NL_022:%.*]] = phi i32 [ [[INC11:%.*]], %[[FOR_END:.*]] ], [ 0, %[[FOR_COND1_PREHEADER_PREHEADER]] ]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_GLOBALDATA:%.*]], ptr @global_data, i64 0, i32 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 16
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 32
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 48
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 64
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 80
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 96
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 112
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP1]], align 4
+; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP2]], align 4
+; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP3]], align 4
+; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x float>, ptr [[TMP4]], align 4
+; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP7]], align 4
+; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x float>, ptr [[TMP8]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, ptr getelementptr inbounds nuw (i8, ptr @global_data, i64 128016), i64 [[INDEX]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP9]], i64 16
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP9]], i64 32
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP9]], i64 48
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP9]], i64 64
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP9]], i64 80
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP9]], i64 96
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP9]], i64 112
+; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x float>, ptr [[TMP9]], align 4
+; CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x float>, ptr [[TMP10]], align 4
+; CHECK-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x float>, ptr [[TMP11]], align 4
+; CHECK-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x float>, ptr [[TMP12]], align 4
+; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <4 x float>, ptr [[TMP13]], align 4
+; CHECK-NEXT: [[WIDE_LOAD13:%.*]] = load <4 x float>, ptr [[TMP14]], align 4
+; CHECK-NEXT: [[WIDE_LOAD14:%.*]] = load <4 x float>, ptr [[TMP15]], align 4
+; CHECK-NEXT: [[WIDE_LOAD15:%.*]] = load <4 x float>, ptr [[TMP16]], align 4
+; CHECK-NEXT: [[TMP17:%.*]] = fadd <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD8]]
+; CHECK-NEXT: [[TMP18:%.*]] = fadd <4 x float> [[WIDE_LOAD1]], [[WIDE_LOAD9]]
+; CHECK-NEXT: [[TMP19:%.*]] = fadd <4 x float> [[WIDE_LOAD2]], [[WIDE_LOAD10]]
+; CHECK-NEXT: [[TMP20:%.*]] = fadd <4 x float> [[WIDE_LOAD3]], [[WIDE_LOAD11]]
+; CHECK-NEXT: [[TMP21:%.*]] = fadd <4 x float> [[WIDE_LOAD4]], [[WIDE_LOAD12]]
+; CHECK-NEXT: [[TMP22:%.*]] = fadd <4 x float> [[WIDE_LOAD5]], [[WIDE_LOAD13]]
+; CHECK-NEXT: [[TMP23:%.*]] = fadd <4 x float> [[WIDE_LOAD6]], [[WIDE_LOAD14]]
+; CHECK-NEXT: [[TMP24:%.*]] = fadd <4 x float> [[WIDE_LOAD7]], [[WIDE_LOAD15]]
+; CHECK-NEXT: [[TMP25:%.*]] = add nsw i64 [[INDEX]], 16000
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_GLOBALDATA]], ptr @global_data, i64 0, i32 0, i64 [[TMP25]]
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP26]], i64 16
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP26]], i64 32
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP26]], i64 48
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP26]], i64 64
+; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP26]], i64 80
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP26]], i64 96
+; CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP26]], i64 112
+; CHECK-NEXT: store <4 x float> [[TMP17]], ptr [[TMP26]], align 4
+; CHECK-NEXT: store <4 x float> [[TMP18]], ptr [[TMP27]], align 4
+; CHECK-NEXT: store <4 x float> [[TMP19]], ptr [[TMP28]], align 4
+; CHECK-NEXT: store <4 x float> [[TMP20]], ptr [[TMP29]], align 4
+; CHECK-NEXT: store <4 x float> [[TMP21]], ptr [[TMP30]], align 4
+; CHECK-NEXT: store <4 x float> [[TMP22]], ptr [[TMP31]], align 4
+; CHECK-NEXT: store <4 x float> [[TMP23]], ptr [[TMP32]], align 4
+; CHECK-NEXT: store <4 x float> [[TMP24]], ptr [[TMP33]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32
+; CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16000
+; CHECK-NEXT: br i1 [[TMP34]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[FOR_END]]
+; CHECK: [[FOR_END]]:
+; CHECK-NEXT: [[INC11]] = add nuw nsw i32 [[NL_022]], 1
+; CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr @ntimes, align 4
+; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP35]], 10
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[INC11]], [[MUL]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_COND1_PREHEADER]], label %[[FOR_END12_LOOPEXIT:.*]]
+; CHECK: [[FOR_END12_LOOPEXIT]]:
+; CHECK-NEXT: br label %[[FOR_END12]]
+; CHECK: [[FOR_END12]]:
+; CHECK-NEXT: ret i32 0
+;
entry:
%0 = load i32, ptr @ntimes, align 4
%cmp21 = icmp sgt i32 %0, 0
@@ -41,11 +130,12 @@ for.end: ; preds = %for.body3
for.end12: ; preds = %for.end, %entry
ret i32 0
-; CHECK-LABEL: @s173
-; CHECK: load <4 x float>, ptr
-; CHECK: add nsw i64 %index, 16000
-; CHECK: ret i32 0
}
attributes #0 = { nounwind }
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+;.
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