[llvm] [LV] Add LoopVectorize/VPlan subdirectory for VPlan printing tests. (PR #180611)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 10 06:57:07 PST 2026
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/180611
>From 632ac8b03afc110c19dba7a656e8e2f076c34852 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Mon, 9 Feb 2026 20:33:09 +0000
Subject: [PATCH 1/2] [LV] Add LoopVectorize/VPlan subdirectory for VPlan
printing tests.
Add a new VPlan subdirectory as common place for tests checking VPlan
printing. It contains a lit.local.cfg that only runs the tests when
assertions are enabled.
This removes the need to add explicit REQUIRES: asserts to VPlan tests.
---
.../{ => VPlan}/first-order-recurrence-chains-vplan.ll | 1 -
.../first-order-recurrence-sink-replicate-region.ll | 1 -
.../{ => VPlan}/interleave-and-scalarize-only.ll | 2 --
llvm/test/Transforms/LoopVectorize/VPlan/lit.local.cfg | 4 ++++
.../LoopVectorize/{ => VPlan}/phi-with-fastflags-vplan.ll | 1 -
.../LoopVectorize/{ => VPlan}/uncountable-early-exit-vplan.ll | 2 --
.../LoopVectorize/{ => VPlan}/vplan-dot-printing.ll | 2 --
.../LoopVectorize/{ => VPlan}/vplan-force-tail-with-evl.ll | 2 --
.../LoopVectorize/{ => VPlan}/vplan-iv-transforms.ll | 0
.../LoopVectorize/{ => VPlan}/vplan-predicate-switch.ll | 1 -
.../LoopVectorize/{ => VPlan}/vplan-print-after-all.ll | 1 -
.../{ => VPlan}/vplan-printing-before-execute.ll | 2 --
.../LoopVectorize/{ => VPlan}/vplan-printing-metadata.ll | 1 -
.../LoopVectorize/{ => VPlan}/vplan-printing-outer-loop.ll | 0
.../LoopVectorize/{ => VPlan}/vplan-printing-reductions.ll | 1 -
.../Transforms/LoopVectorize/{ => VPlan}/vplan-printing.ll | 1 -
.../{ => VPlan}/vplan-sink-scalars-and-merge-vf1.ll | 1 -
.../LoopVectorize/{ => VPlan}/vplan-sink-scalars-and-merge.ll | 2 --
.../{ => VPlan}/vplan-unused-interleave-group.ll | 1 -
.../LoopVectorize/{ => VPlan}/vplan-widen-struct-return.ll | 0
20 files changed, 4 insertions(+), 22 deletions(-)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/first-order-recurrence-chains-vplan.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/first-order-recurrence-sink-replicate-region.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/interleave-and-scalarize-only.ll (99%)
create mode 100644 llvm/test/Transforms/LoopVectorize/VPlan/lit.local.cfg
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/phi-with-fastflags-vplan.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/uncountable-early-exit-vplan.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-dot-printing.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-force-tail-with-evl.ll (98%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-iv-transforms.ll (100%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-predicate-switch.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-print-after-all.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-printing-before-execute.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-printing-metadata.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-printing-outer-loop.ll (100%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-printing-reductions.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-printing.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-sink-scalars-and-merge-vf1.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-sink-scalars-and-merge.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-unused-interleave-group.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan-widen-struct-return.ll (100%)
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll b/llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-chains-vplan.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-chains-vplan.ll
index 9ab2557387877..8d5caf250f3df 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-chains-vplan.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -debug-only=loop-vectorize -disable-output -S %s 2>&1 | FileCheck %s
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
index 6992a441f9444..075faa6a0056f 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
; RUN: opt < %s -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -force-widen-divrem-via-safe-divisor=0 -disable-output -debug-only=loop-vectorize 2>&1 | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll b/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
index 82470d3db0a2f..33294730933e7 100644
--- a/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
@@ -1,5 +1,3 @@
-; REQUIRES: asserts
-
; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -debug -disable-output %s 2>&1 | FileCheck --check-prefix=DBG %s
; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S %s | FileCheck %s
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/lit.local.cfg b/llvm/test/Transforms/LoopVectorize/VPlan/lit.local.cfg
new file mode 100644
index 0000000000000..9861880d9b5bb
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/lit.local.cfg
@@ -0,0 +1,4 @@
+config.suffixes = [".ll"]
+
+if not 'asserts' in config.available_features:
+ config.unsupported = True
diff --git a/llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll b/llvm/test/Transforms/LoopVectorize/VPlan/phi-with-fastflags-vplan.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/phi-with-fastflags-vplan.ll
index e451f94715610..f685bf806929c 100644
--- a/llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/phi-with-fastflags-vplan.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
; RUN: opt -p loop-vectorize -force-vector-width=4 -debug-only=loop-vectorize -disable-output -S %s 2>&1 | FileCheck %s
define void @f(ptr noalias %p, i1 %c) {
diff --git a/llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll b/llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
index be23acd443229..bee97a6955b3a 100644
--- a/llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S -debug %s 2>&1 | FileCheck %s
-; REQUIRES: asserts
-
declare void @init(ptr)
define i64 @multi_exiting_to_different_exits_live_in_exit_values() {
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-dot-printing.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-dot-printing.ll
index ee3564bc87be4..8a93a7a14009f 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-dot-printing.ll
@@ -1,5 +1,3 @@
-; REQUIRES: asserts
-
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -vplan-print-in-dot-format -disable-output %s 2>&1 | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-force-tail-with-evl.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-force-tail-with-evl.ll
similarity index 98%
rename from llvm/test/Transforms/LoopVectorize/vplan-force-tail-with-evl.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-force-tail-with-evl.ll
index f510d47d06e36..dfc3ce13afaef 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-force-tail-with-evl.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-force-tail-with-evl.ll
@@ -1,5 +1,3 @@
-; REQUIRES: asserts
-
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize \
; RUN: -force-tail-folding-style=data-with-evl -force-vector-width=4 \
; RUN: -force-target-supports-scalable-vectors -scalable-vectorization=on \
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-iv-transforms.ll
similarity index 100%
rename from llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-iv-transforms.ll
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-predicate-switch.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-predicate-switch.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
index 917869bf96f02..769c52e80e512 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-predicate-switch.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
@@ -1,4 +1,3 @@
-; REQUIRES: asserts
; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -debug -disable-output %s 2>&1 | FileCheck %s
define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
index 5b68887f0f7da..996be71e2ea90 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
@@ -1,6 +1,5 @@
; RUN: opt -passes=loop-vectorize -disable-output -vplan-print-after-all -force-vector-width=4 -vplan-verify-each < %s 2>&1 | FileCheck %s --implicit-check-not "VPlan after"
; RUN: opt -passes=loop-vectorize -disable-output -vplan-print-after-all -force-vector-width=4 -vplan-verify-each < %s 2>&1 | FileCheck %s --check-prefix CHECK-DUMP
-; REQUIRES: asserts
; Verify that `-vplan-print-after-all` option works.
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-before-execute.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-before-execute.ll
index 9ef3fd48efcd5..cb6937dc3e1ae 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-before-execute.ll
@@ -2,8 +2,6 @@
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-; REQUIRES: asserts
-
; Check if the vector loop condition can be simplified to true for a given
; VF/IC combination.
define void @test_tc_less_than_16(ptr %A, i64 %N) {
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-metadata.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-metadata.ll
index 027bfe859c828..990238b0b1c26 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-metadata.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll
similarity index 100%
rename from llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
index b282a9079c996..0b002ed796374 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -disable-output %s 2>&1 | FileCheck %s
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-printing.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
index 1d5d71b0a64c0..f592c3f8e422d 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -enable-interleaved-mem-accesses=true -enable-masked-interleaved-mem-accesses -force-widen-divrem-via-safe-divisor=0 -disable-output %s 2>&1 | FileCheck --strict-whitespace %s
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge-vf1.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge-vf1.ll
index 3896e67c81b1b..8f4ae4ed3d30a 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge-vf1.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 -debug -disable-output %s 2>&1 | FileCheck %s
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge.ll
index 2f063166b053c..d6d9ab7acd340 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge.ll
@@ -1,5 +1,3 @@
-; REQUIRES: asserts
-
; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=2 -force-widen-divrem-via-safe-divisor=0 -debug -disable-output %s 2>&1 | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-unused-interleave-group.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-unused-interleave-group.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-unused-interleave-group.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-unused-interleave-group.ll
index 6ca7a1f9fd02f..e62c6f16617b1 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-unused-interleave-group.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-unused-interleave-group.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=loop-vectorize -S -force-vector-width=4 -enable-interleaved-mem-accesses=true -debug-only=loop-vectorize --disable-output < %s 2>&1 | FileCheck %s
-; REQUIRES: asserts
; This test checks if an unused interleave group is removed by removeDeadRecipes.
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-widen-struct-return.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-widen-struct-return.ll
similarity index 100%
rename from llvm/test/Transforms/LoopVectorize/vplan-widen-struct-return.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-widen-struct-return.ll
>From b884c947533da59445b265a40f0c8167372e20de Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Tue, 10 Feb 2026 14:34:21 +0000
Subject: [PATCH 2/2] !fixup move more test
---
llvm/test/Transforms/LoopVectorize/VPlan/AArch64/lit.local.cfg | 2 ++
.../{ => VPlan}/AArch64/sve-tail-folding-forced.ll | 1 -
.../LoopVectorize/{ => VPlan}/AArch64/sve2-histcnt-vplan.ll | 1 -
.../LoopVectorize/{ => VPlan}/AArch64/vplan-printing.ll | 1 -
.../{ => VPlan}/AArch64/widen-call-with-intrinsic-or-libfunc.ll | 1 -
llvm/test/Transforms/LoopVectorize/VPlan/PowerPC/lit.local.cfg | 2 ++
.../{ => VPlan}/PowerPC/vplan-force-tail-with-evl.ll | 2 --
llvm/test/Transforms/LoopVectorize/VPlan/RISCV/lit.local.cfg | 2 ++
.../{ => VPlan}/RISCV/vplan-riscv-vector-reverse.ll | 1 -
.../RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll | 2 --
.../{ => VPlan}/RISCV/vplan-vp-intrinsics-reduction.ll | 2 --
llvm/test/Transforms/LoopVectorize/VPlan/X86/lit.local.cfg | 2 ++
.../LoopVectorize/{ => VPlan}/X86/vplan-vp-intrinsics.ll | 2 --
.../{ => VPlan}/conditional-scalar-assignment-vplan.ll | 0
llvm/test/Transforms/LoopVectorize/{ => VPlan}/icmp-uniforms.ll | 0
.../LoopVectorize/{ => VPlan}/vplan_hcfg_stress_test.ll | 0
16 files changed, 8 insertions(+), 13 deletions(-)
create mode 100644 llvm/test/Transforms/LoopVectorize/VPlan/AArch64/lit.local.cfg
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/AArch64/sve-tail-folding-forced.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/AArch64/sve2-histcnt-vplan.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/AArch64/vplan-printing.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/AArch64/widen-call-with-intrinsic-or-libfunc.ll (99%)
create mode 100644 llvm/test/Transforms/LoopVectorize/VPlan/PowerPC/lit.local.cfg
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/PowerPC/vplan-force-tail-with-evl.ll (99%)
create mode 100644 llvm/test/Transforms/LoopVectorize/VPlan/RISCV/lit.local.cfg
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/RISCV/vplan-riscv-vector-reverse.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/RISCV/vplan-vp-intrinsics-reduction.ll (99%)
create mode 100644 llvm/test/Transforms/LoopVectorize/VPlan/X86/lit.local.cfg
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/X86/vplan-vp-intrinsics.ll (99%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/conditional-scalar-assignment-vplan.ll (100%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/icmp-uniforms.ll (100%)
rename llvm/test/Transforms/LoopVectorize/{ => VPlan}/vplan_hcfg_stress_test.ll (100%)
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/lit.local.cfg b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/lit.local.cfg
new file mode 100644
index 0000000000000..10d4a0e953ed4
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "AArch64" in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
index 1c4b8d61d167e..2db9717e30ec6 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter-out-after "^scalar.ph:"
-; REQUIRES: asserts
; RUN: opt -S -passes=loop-vectorize -debug-only=loop-vectorize < %s 2>%t | FileCheck %s
; RUN: cat %t | FileCheck %s --check-prefix=VPLANS
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve2-histcnt-vplan.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve2-histcnt-vplan.ll
index 9891617890625..386831008e147 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve2-histcnt-vplan.ll
@@ -1,5 +1,4 @@
; RUN: opt < %s -mattr=+sve2 -passes=loop-vectorize,instcombine -enable-histogram-loop-vectorization -sve-gather-overhead=2 -sve-scatter-overhead=2 -force-vector-interleave=1 -debug-only=loop-vectorize --disable-output -S 2>&1 | FileCheck %s
-; REQUIRES: asserts
target triple = "aarch64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
index 65a1a6e64a40e..d30bf1928808c 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
@@ -1,4 +1,3 @@
-; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -disable-output %s 2>&1 | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/widen-call-with-intrinsic-or-libfunc.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/AArch64/widen-call-with-intrinsic-or-libfunc.ll
index cf035d0b2b2ee..c71628393f982 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/widen-call-with-intrinsic-or-libfunc.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter-out-after "scalar.ph:"
-; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -vectorizer-maximize-bandwidth -mtriple=arm64-apple-ios -debug -S %s 2>&1 | FileCheck %s
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/PowerPC/lit.local.cfg b/llvm/test/Transforms/LoopVectorize/VPlan/PowerPC/lit.local.cfg
new file mode 100644
index 0000000000000..bb982488eb15e
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/PowerPC/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "PowerPC" in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll b/llvm/test/Transforms/LoopVectorize/VPlan/PowerPC/vplan-force-tail-with-evl.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/PowerPC/vplan-force-tail-with-evl.ll
index a51fe3248f90e..374551321bcf7 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/PowerPC/vplan-force-tail-with-evl.ll
@@ -1,5 +1,3 @@
-; REQUIRES: asserts
-
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize \
; RUN: -force-tail-folding-style=data-with-evl \
; RUN: -prefer-predicate-over-epilogue=predicate-dont-vectorize \
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/lit.local.cfg b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/lit.local.cfg
new file mode 100644
index 0000000000000..17351748513d9
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "RISCV" in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/vplan-riscv-vector-reverse.ll b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/RISCV/vplan-riscv-vector-reverse.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
index 8b6ce538474c7..e58577473320e 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/vplan-riscv-vector-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
@@ -4,7 +4,6 @@
; for (int i = N-1; i >= 0; --i)
; a[i] = b[i] + 1.0;
-; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v \
; RUN: -debug-only=loop-vectorize -scalable-vectorization=on \
; RUN: -disable-output < %s 2>&1 | FileCheck %s
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
index cc76ea04978a3..43c0367e99a8a 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
@@ -1,5 +1,3 @@
-; REQUIRES: asserts
-
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize \
; RUN: -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue \
; RUN: -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -disable-output < %s 2>&1 | FileCheck --check-prefix=IF-EVL %s
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll
index a3293366c17bc..8e2c4ff419c4c 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll
@@ -1,5 +1,3 @@
-; REQUIRES: asserts
-
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize \
; RUN: -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue \
; RUN: -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -disable-output < %s 2>&1 | FileCheck --check-prefixes=IF-EVL-OUTLOOP,IF-EVL %s
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/X86/lit.local.cfg b/llvm/test/Transforms/LoopVectorize/VPlan/X86/lit.local.cfg
new file mode 100644
index 0000000000000..42bf50dcc13c3
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/X86/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "X86" in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/Transforms/LoopVectorize/X86/vplan-vp-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/VPlan/X86/vplan-vp-intrinsics.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/X86/vplan-vp-intrinsics.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/X86/vplan-vp-intrinsics.ll
index 327df6a2cbf8a..a72caee64ee60 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/vplan-vp-intrinsics.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/X86/vplan-vp-intrinsics.ll
@@ -1,5 +1,3 @@
-; REQUIRES: asserts
-
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-width=4 \
; RUN: -force-tail-folding-style=data-with-evl \
; RUN: -prefer-predicate-over-epilogue=predicate-dont-vectorize \
diff --git a/llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-vplan.ll b/llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
similarity index 100%
rename from llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-vplan.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
diff --git a/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll b/llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
similarity index 100%
rename from llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
diff --git a/llvm/test/Transforms/LoopVectorize/vplan_hcfg_stress_test.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan_hcfg_stress_test.ll
similarity index 100%
rename from llvm/test/Transforms/LoopVectorize/vplan_hcfg_stress_test.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan_hcfg_stress_test.ll
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