[llvm] [RISCV] Refactor the MC layer SiFive VCIX classes. (PR #180433)

[Brandon Wu via llvm-commits]

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@@ -49,124 +72,141 @@ def tsimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
   let OperandType = "OPERAND_SIMM5";
 }
 
-class SwapVCIXIns<dag funct6, dag rd, dag rs2, dag rs1, bit swap> {
-  dag Ins = !con(funct6, !if(swap, rs2, rd), !if(swap, rd, rs2), rs1);
+class VCIXInfo<VCIXType type, VCIXRs1Info rs1info, bit HaveOutputDst> {
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4vtomat wrote:

should this be HasOutputDst? Or all lower case to follow other arguments


https://github.com/llvm/llvm-project/pull/180433