[llvm] [AMDGPU] Fix LDS address correction in promoteConstantOffsetToImm for async stores (PR #180220)

[Jay Foad via llvm-commits]

================
@@ -2369,24 +2369,30 @@ void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base
   Addr.Offset = (*Offset0P & 0x00000000ffffffff) | (Offset1 << 32);
 }
 
-// Maintain the correct LDS address for async loads.
-// It becomes incorrect when promoteConstantOffsetToImm
-// adds an offset only meant for the src operand.
+// Maintain the correct LDS address for async loads and stores.
+// It becomes incorrect when promoteConstantOffsetToImm adds an offset only
+// meant for the global address operand. For async loads the LDS address is in
+// vdst. For async stores, the LDS address is in vdata.
 void SILoadStoreOptimizer::updateAsyncLDSAddress(MachineInstr &MI,
                                                  int32_t OffsetDiff) const {
   if (!TII->usesASYNC_CNT(MI) || OffsetDiff == 0)
     return;
 
-  Register OldVDst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg();
-  Register NewVDst = MRI->createVirtualRegister(MRI->getRegClass(OldVDst));
+  MachineOperand *LDSAddr = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
+  if (!LDSAddr)
+    LDSAddr = TII->getNamedOperand(MI, AMDGPU::OpName::vdata);
----------------
jayfoad wrote:

Just a style nit, maybe neater to distinguish based on MI.mayLoad rather than relying on a named operand lookup failing?
```suggestion
  MachineOperand *LDSAddr = TII->getNamedOperand(MI, MI.mayLoad() ? AMDGPU::OpName::vdst : AMDGPU::OpName::vdata);
```

https://github.com/llvm/llvm-project/pull/180220