[llvm] 4dc4abc - [AArch64][GlobalISel] Add test coverage for arm64-neon-2velem-high.ll and mla_mls_merge.ll. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 10 05:59:57 PST 2026
Author: David Green
Date: 2026-02-10T13:59:51Z
New Revision: 4dc4abc09453fa8ea2a3d38783261f50f0be8c40
URL: https://github.com/llvm/llvm-project/commit/4dc4abc09453fa8ea2a3d38783261f50f0be8c40
DIFF: https://github.com/llvm/llvm-project/commit/4dc4abc09453fa8ea2a3d38783261f50f0be8c40.diff
LOG: [AArch64][GlobalISel] Add test coverage for arm64-neon-2velem-high.ll and mla_mls_merge.ll. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
llvm/test/CodeGen/AArch64/mla_mls_merge.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll b/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
index f1678ca19f47d..7581671a51f60 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
@@ -1,13 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast \
-; RUN: < %s -verify-machineinstrs | FileCheck %s
+; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast < %s -verify-machineinstrs -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for test_vfms_n_f32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vfmsq_n_f32
define <4 x i32> @test_vmull_high_n_s16(<8 x i16> %a, i16 %b) #0 {
-; CHECK-LABEL: test_vmull_high_n_s16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v1.8h, w0
-; CHECK-NEXT: smull2 v0.4s, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmull_high_n_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v1.8h, w0
+; CHECK-SD-NEXT: smull2 v0.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmull_high_n_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: dup v1.4h, w0
+; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 0
@@ -19,11 +29,18 @@ entry:
}
define <4 x i32> @test_vmull_high_n_s16_imm(<8 x i16> %a) #0 {
-; CHECK-LABEL: test_vmull_high_n_s16_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v1.8h, #29
-; CHECK-NEXT: smull2 v0.4s, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmull_high_n_s16_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v1.8h, #29
+; CHECK-SD-NEXT: smull2 v0.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmull_high_n_s16_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.4h, #29
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -31,11 +48,18 @@ entry:
}
define <2 x i64> @test_vmull_high_n_s32(<4 x i32> %a, i32 %b) #0 {
-; CHECK-LABEL: test_vmull_high_n_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v1.4s, w0
-; CHECK-NEXT: smull2 v0.2d, v0.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmull_high_n_s32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v1.4s, w0
+; CHECK-SD-NEXT: smull2 v0.2d, v0.4s, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmull_high_n_s32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: dup v1.2s, w0
+; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 0
@@ -45,11 +69,18 @@ entry:
}
define <2 x i64> @test_vmull_high_n_s32_imm(<4 x i32> %a) #0 {
-; CHECK-LABEL: test_vmull_high_n_s32_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v1.4s, #1, msl #8
-; CHECK-NEXT: smull2 v0.2d, v0.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmull_high_n_s32_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v1.4s, #1, msl #8
+; CHECK-SD-NEXT: smull2 v0.2d, v0.4s, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmull_high_n_s32_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2s, #1, msl #8
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 511, i32 511>)
@@ -57,11 +88,18 @@ entry:
}
define <4 x i32> @test_vmull_high_n_u16(<8 x i16> %a, i16 %b) #0 {
-; CHECK-LABEL: test_vmull_high_n_u16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v1.8h, w0
-; CHECK-NEXT: umull2 v0.4s, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmull_high_n_u16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v1.8h, w0
+; CHECK-SD-NEXT: umull2 v0.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmull_high_n_u16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: dup v1.4h, w0
+; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 0
@@ -73,11 +111,18 @@ entry:
}
define <4 x i32> @test_vmull_high_n_u16_imm(<8 x i16> %a) #0 {
-; CHECK-LABEL: test_vmull_high_n_u16_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v1.8h, #17, lsl #8
-; CHECK-NEXT: umull2 v0.4s, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmull_high_n_u16_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v1.8h, #17, lsl #8
+; CHECK-SD-NEXT: umull2 v0.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmull_high_n_u16_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.4h, #17, lsl #8
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 4352, i16 4352, i16 4352, i16 4352>)
@@ -85,11 +130,18 @@ entry:
}
define <2 x i64> @test_vmull_high_n_u32(<4 x i32> %a, i32 %b) #0 {
-; CHECK-LABEL: test_vmull_high_n_u32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v1.4s, w0
-; CHECK-NEXT: umull2 v0.2d, v0.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmull_high_n_u32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v1.4s, w0
+; CHECK-SD-NEXT: umull2 v0.2d, v0.4s, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmull_high_n_u32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: dup v1.2s, w0
+; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 0
@@ -99,11 +151,18 @@ entry:
}
define <2 x i64> @test_vmull_high_n_u32_imm(<4 x i32> %a) #0 {
-; CHECK-LABEL: test_vmull_high_n_u32_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mvni v1.4s, #1, msl #8
-; CHECK-NEXT: umull2 v0.2d, v0.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmull_high_n_u32_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mvni v1.4s, #1, msl #8
+; CHECK-SD-NEXT: umull2 v0.2d, v0.4s, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmull_high_n_u32_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: mvni v1.2s, #1, msl #8
+; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 4294966784, i32 4294966784>)
@@ -111,11 +170,18 @@ entry:
}
define <4 x i32> @test_vqdmull_high_n_s16(<8 x i16> %a, i16 %b) #0 {
-; CHECK-LABEL: test_vqdmull_high_n_s16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v1.8h, w0
-; CHECK-NEXT: sqdmull2 v0.4s, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmull_high_n_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v1.8h, w0
+; CHECK-SD-NEXT: sqdmull2 v0.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmull_high_n_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: dup v1.4h, w0
+; CHECK-GI-NEXT: sqdmull v0.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 0
@@ -127,11 +193,18 @@ entry:
}
define <4 x i32> @test_vqdmull_high_n_s16_imm(<8 x i16> %a) #0 {
-; CHECK-LABEL: test_vqdmull_high_n_s16_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mvni v1.8h, #17, lsl #8
-; CHECK-NEXT: sqdmull2 v0.4s, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmull_high_n_s16_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mvni v1.8h, #17, lsl #8
+; CHECK-SD-NEXT: sqdmull2 v0.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmull_high_n_s16_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: mvni v1.4h, #17, lsl #8
+; CHECK-GI-NEXT: sqdmull v0.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 61183, i16 61183, i16 61183, i16 61183>)
@@ -139,11 +212,18 @@ entry:
}
define <2 x i64> @test_vqdmull_high_n_s32(<4 x i32> %a, i32 %b) #0 {
-; CHECK-LABEL: test_vqdmull_high_n_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v1.4s, w0
-; CHECK-NEXT: sqdmull2 v0.2d, v0.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmull_high_n_s32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v1.4s, w0
+; CHECK-SD-NEXT: sqdmull2 v0.2d, v0.4s, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmull_high_n_s32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: dup v1.2s, w0
+; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 0
@@ -153,11 +233,18 @@ entry:
}
define <2 x i64> @test_vqdmull_high_n_s32_imm(<4 x i32> %a) #0 {
-; CHECK-LABEL: test_vqdmull_high_n_s32_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v1.4s, #29
-; CHECK-NEXT: sqdmull2 v0.2d, v0.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmull_high_n_s32_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v1.4s, #29
+; CHECK-SD-NEXT: sqdmull2 v0.2d, v0.4s, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmull_high_n_s32_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2s, #29
+; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -165,11 +252,18 @@ entry:
}
define <4 x i32> @test_vmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
-; CHECK-LABEL: test_vmlal_high_n_s16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.8h, w0
-; CHECK-NEXT: smlal2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlal_high_n_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.8h, w0
+; CHECK-SD-NEXT: smlal2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlal_high_n_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.4h, w0
+; CHECK-GI-NEXT: smlal v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -182,11 +276,18 @@ entry:
}
define <4 x i32> @test_vmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
-; CHECK-LABEL: test_vmlal_high_n_s16_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.8h, #29
-; CHECK-NEXT: smlal2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlal_high_n_s16_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.8h, #29
+; CHECK-SD-NEXT: smlal2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlal_high_n_s16_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4h, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: smlal v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -195,11 +296,18 @@ entry:
}
define <2 x i64> @test_vmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
-; CHECK-LABEL: test_vmlal_high_n_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.4s, w0
-; CHECK-NEXT: smlal2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlal_high_n_s32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.4s, w0
+; CHECK-SD-NEXT: smlal2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlal_high_n_s32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.2s, w0
+; CHECK-GI-NEXT: smlal v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -210,11 +318,18 @@ entry:
}
define <2 x i64> @test_vmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
-; CHECK-LABEL: test_vmlal_high_n_s32_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.4s, #29
-; CHECK-NEXT: smlal2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlal_high_n_s32_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.4s, #29
+; CHECK-SD-NEXT: smlal2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlal_high_n_s32_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2s, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: smlal v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -223,11 +338,18 @@ entry:
}
define <4 x i32> @test_vmlal_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
-; CHECK-LABEL: test_vmlal_high_n_u16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.8h, w0
-; CHECK-NEXT: umlal2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlal_high_n_u16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.8h, w0
+; CHECK-SD-NEXT: umlal2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlal_high_n_u16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.4h, w0
+; CHECK-GI-NEXT: umlal v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -240,11 +362,18 @@ entry:
}
define <4 x i32> @test_vmlal_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
-; CHECK-LABEL: test_vmlal_high_n_u16_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.8h, #29
-; CHECK-NEXT: umlal2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlal_high_n_u16_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.8h, #29
+; CHECK-SD-NEXT: umlal2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlal_high_n_u16_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4h, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: umlal v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -253,11 +382,18 @@ entry:
}
define <2 x i64> @test_vmlal_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
-; CHECK-LABEL: test_vmlal_high_n_u32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.4s, w0
-; CHECK-NEXT: umlal2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlal_high_n_u32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.4s, w0
+; CHECK-SD-NEXT: umlal2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlal_high_n_u32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.2s, w0
+; CHECK-GI-NEXT: umlal v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -268,11 +404,18 @@ entry:
}
define <2 x i64> @test_vmlal_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
-; CHECK-LABEL: test_vmlal_high_n_u32_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.4s, #29
-; CHECK-NEXT: umlal2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlal_high_n_u32_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.4s, #29
+; CHECK-SD-NEXT: umlal2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlal_high_n_u32_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2s, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: umlal v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -281,11 +424,18 @@ entry:
}
define <4 x i32> @test_vqdmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
-; CHECK-LABEL: test_vqdmlal_high_n_s16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.8h, w0
-; CHECK-NEXT: sqdmlal2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmlal_high_n_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.8h, w0
+; CHECK-SD-NEXT: sqdmlal2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmlal_high_n_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.4h, w0
+; CHECK-GI-NEXT: sqdmlal v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -298,11 +448,18 @@ entry:
}
define <4 x i32> @test_vqdmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
-; CHECK-LABEL: test_vqdmlal_high_n_s16_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.8h, #29
-; CHECK-NEXT: sqdmlal2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmlal_high_n_s16_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.8h, #29
+; CHECK-SD-NEXT: sqdmlal2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmlal_high_n_s16_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4h, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: sqdmlal v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -311,11 +468,18 @@ entry:
}
define <2 x i64> @test_vqdmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
-; CHECK-LABEL: test_vqdmlal_high_n_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.4s, w0
-; CHECK-NEXT: sqdmlal2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmlal_high_n_s32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.4s, w0
+; CHECK-SD-NEXT: sqdmlal2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmlal_high_n_s32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.2s, w0
+; CHECK-GI-NEXT: sqdmlal v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -326,11 +490,18 @@ entry:
}
define <2 x i64> @test_vqdmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
-; CHECK-LABEL: test_vqdmlal_high_n_s32_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.4s, #29
-; CHECK-NEXT: sqdmlal2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmlal_high_n_s32_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.4s, #29
+; CHECK-SD-NEXT: sqdmlal2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmlal_high_n_s32_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2s, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: sqdmlal v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -339,11 +510,18 @@ entry:
}
define <4 x i32> @test_vmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
-; CHECK-LABEL: test_vmlsl_high_n_s16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.8h, w0
-; CHECK-NEXT: smlsl2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlsl_high_n_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.8h, w0
+; CHECK-SD-NEXT: smlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlsl_high_n_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.4h, w0
+; CHECK-GI-NEXT: smlsl v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -356,11 +534,18 @@ entry:
}
define <4 x i32> @test_vmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
-; CHECK-LABEL: test_vmlsl_high_n_s16_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.8h, #29
-; CHECK-NEXT: smlsl2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlsl_high_n_s16_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.8h, #29
+; CHECK-SD-NEXT: smlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlsl_high_n_s16_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4h, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: smlsl v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -369,11 +554,18 @@ entry:
}
define <2 x i64> @test_vmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
-; CHECK-LABEL: test_vmlsl_high_n_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.4s, w0
-; CHECK-NEXT: smlsl2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlsl_high_n_s32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.4s, w0
+; CHECK-SD-NEXT: smlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlsl_high_n_s32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.2s, w0
+; CHECK-GI-NEXT: smlsl v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -384,11 +576,18 @@ entry:
}
define <2 x i64> @test_vmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
-; CHECK-LABEL: test_vmlsl_high_n_s32_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.4s, #29
-; CHECK-NEXT: smlsl2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlsl_high_n_s32_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.4s, #29
+; CHECK-SD-NEXT: smlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlsl_high_n_s32_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2s, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: smlsl v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -397,11 +596,18 @@ entry:
}
define <4 x i32> @test_vmlsl_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
-; CHECK-LABEL: test_vmlsl_high_n_u16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.8h, w0
-; CHECK-NEXT: umlsl2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlsl_high_n_u16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.8h, w0
+; CHECK-SD-NEXT: umlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlsl_high_n_u16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.4h, w0
+; CHECK-GI-NEXT: umlsl v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -414,11 +620,18 @@ entry:
}
define <4 x i32> @test_vmlsl_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
-; CHECK-LABEL: test_vmlsl_high_n_u16_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.8h, #29
-; CHECK-NEXT: umlsl2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlsl_high_n_u16_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.8h, #29
+; CHECK-SD-NEXT: umlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlsl_high_n_u16_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4h, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: umlsl v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -427,11 +640,18 @@ entry:
}
define <2 x i64> @test_vmlsl_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
-; CHECK-LABEL: test_vmlsl_high_n_u32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.4s, w0
-; CHECK-NEXT: umlsl2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlsl_high_n_u32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.4s, w0
+; CHECK-SD-NEXT: umlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlsl_high_n_u32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.2s, w0
+; CHECK-GI-NEXT: umlsl v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -442,11 +662,18 @@ entry:
}
define <2 x i64> @test_vmlsl_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
-; CHECK-LABEL: test_vmlsl_high_n_u32_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.4s, #29
-; CHECK-NEXT: umlsl2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vmlsl_high_n_u32_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.4s, #29
+; CHECK-SD-NEXT: umlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmlsl_high_n_u32_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2s, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: umlsl v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -455,11 +682,18 @@ entry:
}
define <4 x i32> @test_vqdmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
-; CHECK-LABEL: test_vqdmlsl_high_n_s16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.8h, w0
-; CHECK-NEXT: sqdmlsl2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmlsl_high_n_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.8h, w0
+; CHECK-SD-NEXT: sqdmlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmlsl_high_n_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.4h, w0
+; CHECK-GI-NEXT: sqdmlsl v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -472,11 +706,18 @@ entry:
}
define <4 x i32> @test_vqdmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
-; CHECK-LABEL: test_vqdmlsl_high_n_s16_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.8h, #29
-; CHECK-NEXT: sqdmlsl2 v0.4s, v1.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmlsl_high_n_s16_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.8h, #29
+; CHECK-SD-NEXT: sqdmlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmlsl_high_n_s16_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4h, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: sqdmlsl v0.4s, v1.4h, v2.4h
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -485,11 +726,18 @@ entry:
}
define <2 x i64> @test_vqdmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
-; CHECK-LABEL: test_vqdmlsl_high_n_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: dup v2.4s, w0
-; CHECK-NEXT: sqdmlsl2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmlsl_high_n_s32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: dup v2.4s, w0
+; CHECK-SD-NEXT: sqdmlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmlsl_high_n_s32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: dup v2.2s, w0
+; CHECK-GI-NEXT: sqdmlsl v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -500,11 +748,18 @@ entry:
}
define <2 x i64> @test_vqdmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
-; CHECK-LABEL: test_vqdmlsl_high_n_s32_imm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.4s, #29
-; CHECK-NEXT: sqdmlsl2 v0.2d, v1.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqdmlsl_high_n_s32_imm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.4s, #29
+; CHECK-SD-NEXT: sqdmlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqdmlsl_high_n_s32_imm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2s, #29
+; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: sqdmlsl v0.2d, v1.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vqdmlsl9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
diff --git a/llvm/test/CodeGen/AArch64/mla_mls_merge.ll b/llvm/test/CodeGen/AArch64/mla_mls_merge.ll
index 17abaf387c180..e1efd636b0461 100644
--- a/llvm/test/CodeGen/AArch64/mla_mls_merge.ll
+++ b/llvm/test/CodeGen/AArch64/mla_mls_merge.ll
@@ -1,13 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-unknown-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <4 x i16> @test_mla0(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {
-; CHECK-LABEL: test_mla0:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: umull v2.8h, v2.8b, v3.8b
-; CHECK-NEXT: umlal v2.8h, v0.8b, v1.8b
-; CHECK-NEXT: fmov d0, d2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_mla0:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: umull v2.8h, v2.8b, v3.8b
+; CHECK-SD-NEXT: umlal v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov d0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_mla0:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: umull v0.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: umlal v0.8h, v2.8b, v3.8b
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%vmull.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %a, <8 x i8> %b)
%vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %c, <8 x i8> %d)
@@ -16,14 +24,20 @@ entry:
ret <4 x i16> %shuffle.i
}
-
define <4 x i16> @test_mla1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {
-; CHECK-LABEL: test_mla1:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: smull v2.8h, v2.8b, v3.8b
-; CHECK-NEXT: smlal v2.8h, v0.8b, v1.8b
-; CHECK-NEXT: fmov d0, d2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_mla1:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: smull v2.8h, v2.8b, v3.8b
+; CHECK-SD-NEXT: smlal v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov d0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_mla1:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: smull v0.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: smlal v0.8h, v2.8b, v3.8b
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%vmull.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %a, <8 x i8> %b)
%vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %c, <8 x i8> %d)
@@ -32,14 +46,20 @@ entry:
ret <4 x i16> %shuffle.i
}
-
define <2 x i32> @test_mla2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) {
-; CHECK-LABEL: test_mla2:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: umull v2.4s, v2.4h, v3.4h
-; CHECK-NEXT: umlal v2.4s, v0.4h, v1.4h
-; CHECK-NEXT: fmov d0, d2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_mla2:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: umull v2.4s, v2.4h, v3.4h
+; CHECK-SD-NEXT: umlal v2.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: fmov d0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_mla2:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: umlal v0.4s, v2.4h, v3.4h
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %a, <4 x i16> %b)
%vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %c, <4 x i16> %d)
@@ -48,14 +68,20 @@ entry:
ret <2 x i32> %shuffle.i
}
-
define <2 x i32> @test_mla3(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) {
-; CHECK-LABEL: test_mla3:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: smull v2.4s, v2.4h, v3.4h
-; CHECK-NEXT: smlal v2.4s, v0.4h, v1.4h
-; CHECK-NEXT: fmov d0, d2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_mla3:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: smull v2.4s, v2.4h, v3.4h
+; CHECK-SD-NEXT: smlal v2.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: fmov d0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_mla3:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: smlal v0.4s, v2.4h, v3.4h
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %a, <4 x i16> %b)
%vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %c, <4 x i16> %d)
@@ -64,14 +90,20 @@ entry:
ret <2 x i32> %shuffle.i
}
-
define <1 x i64> @test_mla4(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {
-; CHECK-LABEL: test_mla4:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: umull v2.2d, v2.2s, v3.2s
-; CHECK-NEXT: umlal v2.2d, v0.2s, v1.2s
-; CHECK-NEXT: fmov d0, d2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_mla4:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: umull v2.2d, v2.2s, v3.2s
+; CHECK-SD-NEXT: umlal v2.2d, v0.2s, v1.2s
+; CHECK-SD-NEXT: fmov d0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_mla4:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: umlal v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %a, <2 x i32> %b)
%vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %c, <2 x i32> %d)
@@ -80,14 +112,20 @@ entry:
ret <1 x i64> %shuffle.i
}
-
define <1 x i64> @test_mla5(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {
-; CHECK-LABEL: test_mla5:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: smull v2.2d, v2.2s, v3.2s
-; CHECK-NEXT: smlal v2.2d, v0.2s, v1.2s
-; CHECK-NEXT: fmov d0, d2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_mla5:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: smull v2.2d, v2.2s, v3.2s
+; CHECK-SD-NEXT: smlal v2.2d, v0.2s, v1.2s
+; CHECK-SD-NEXT: fmov d0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_mla5:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: smlal v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %a, <2 x i32> %b)
%vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %c, <2 x i32> %d)
@@ -96,7 +134,6 @@ entry:
ret <1 x i64> %shuffle.i
}
-
define <4 x i16> @test_mls0(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {
; CHECK-LABEL: test_mls0:
; CHECK: // %bb.0: // %entry
@@ -112,7 +149,6 @@ entry:
ret <4 x i16> %shuffle.i
}
-
define <4 x i16> @test_mls1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {
; CHECK-LABEL: test_mls1:
; CHECK: // %bb.0: // %entry
@@ -128,7 +164,6 @@ entry:
ret <4 x i16> %shuffle.i
}
-
define <2 x i32> @test_mls2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) {
; CHECK-LABEL: test_mls2:
; CHECK: // %bb.0: // %entry
@@ -144,7 +179,6 @@ entry:
ret <2 x i32> %shuffle.i
}
-
define <2 x i32> @test_mls3(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) {
; CHECK-LABEL: test_mls3:
; CHECK: // %bb.0: // %entry
@@ -160,7 +194,6 @@ entry:
ret <2 x i32> %shuffle.i
}
-
define <1 x i64> @test_mls4(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {
; CHECK-LABEL: test_mls4:
; CHECK: // %bb.0: // %entry
@@ -176,7 +209,6 @@ entry:
ret <1 x i64> %shuffle.i
}
-
define <1 x i64> @test_mls5(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {
; CHECK-LABEL: test_mls5:
; CHECK: // %bb.0: // %entry
@@ -191,15 +223,3 @@ entry:
%shuffle.i = shufflevector <2 x i64> %sub.i, <2 x i64> undef, <1 x i32> zeroinitializer
ret <1 x i64> %shuffle.i
}
-
-declare <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8>, <8 x i8>)
-
-declare <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8>, <8 x i8>)
-
-declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>)
-
-declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>)
-
-declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>)
-
-declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>)
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