[llvm] [AArch64] Lower factor-of-2 interleaved stores to STNP (PR #177938)

[Florian Hahn via llvm-commits]

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@@ -18465,6 +18465,43 @@ bool hasNearbyPairedStore(Iter It, Iter End, Value *Ptr, const DataLayout &DL) {
   return false;
 }
 
+// Coordinated with STNP handling in
+// `llvm/lib/Target/AArch64/AArch64InstrInfo.td` and
+// `LowerNTStore`
+static bool isLegalNTStore(Type *DataType, Align Alignment,
+                           const DataLayout &DL) {
+  // Currently we only support NT stores lowering for little-endian targets.
+  if (!DL.isLittleEndian())
+    return false;
+
+  // The backend can lower to STNPWi in this case
+  if (DataType->isIntegerTy(64))
+    return true;
+
+  if (auto *DataTypeTy = dyn_cast<FixedVectorType>(DataType)) {
+    unsigned NumElements = DataTypeTy->getNumElements();
+    unsigned EltSizeBits = DataTypeTy->getElementType()->getScalarSizeInBits();
+    unsigned TotalSizeBits =
+        DataTypeTy->getPrimitiveSizeInBits().getFixedValue();
+
+    // Currently only power-of-2 vectors are supported
+    if (!isPowerOf2_64(NumElements) || !isPowerOf2_64(EltSizeBits))
+      return false;
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fhahn wrote:

can move just above, where we define `NumElements`

https://github.com/llvm/llvm-project/pull/177938