[llvm] [AArch64][ISel] Add clmul to pmullb/t lowering (PR #180568)

[Matthew Devereau via llvm-commits]

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@@ -4254,6 +4254,17 @@ let Predicates = [HasSVEAES, HasNonStreamingSVE_or_SSVE_AES] in {
   defm PMULLT_ZZZ_Q : sve2_wide_int_arith_pmul<0b00, 0b11011, "pmullt", int_aarch64_sve_pmullt_pair>;
 }
 
+let Predicates = [HasSVEAES, HasSVE2_or_SME] in {
+  def : Pat<(nxv2i64 (clmul nxv2i64:$Rn, nxv2i64:$Rm)),
+            (ZIP1_ZZZ_D (UZP1_ZZZ_D (PMULLB_ZZZ_Q $Rn, $Rm), (PMULLT_ZZZ_Q $Rn, $Rm)),
+                        (UZP1_ZZZ_D (PMULLT_ZZZ_Q $Rn, $Rm), (PMULLT_ZZZ_Q $Rn, $Rm)))>;
+}
+let Predicates = [HasSVE2_or_SME] in {
+  def : Pat<(nxv4i32 (clmul nxv4i32:$Rn, nxv4i32:$Rm)),
+            (ZIP1_ZZZ_S (UZP1_ZZZ_S (PMULLB_ZZZ_D $Rn, $Rm), (PMULLT_ZZZ_D $Rn, $Rm)),
+                        (UZP1_ZZZ_S (PMULLT_ZZZ_D $Rn, $Rm), (PMULLT_ZZZ_D $Rn, $Rm)))>;
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MDevereau wrote:

> Not sure if this is what you mean but CLMUL and PMUL are the same operation. Presumably, because PMUL only operates on i8 operands, Matt is using the long variants, which support i32 operands, with the shuffles concatenating the lower "operand" sized results. Much like a normal multiply (i.e. MUL (mul) and MULL (mul long)) the bottom "operand" sized result bits are identical.

Yes, that's bang on.

> Regarding the shuffles. Assuming you want to extract and interleave the bottom half of each element, I think a single trn1 should work?

I'll give that a go and push it if it works, thank you.

https://github.com/llvm/llvm-project/pull/180568