[llvm] dca7b11 - [X86] Add tests showing failure to reduce the vector width of vpmaddwd/vpmaddubsw/pmulhrsw nodes (#180728)
via llvm-commits
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Tue Feb 10 04:45:27 PST 2026
Author: Simon Pilgrim
Date: 2026-02-10T12:45:21Z
New Revision: dca7b11a326f523a93268dd17e969d1c26bcf40e
URL: https://github.com/llvm/llvm-project/commit/dca7b11a326f523a93268dd17e969d1c26bcf40e
DIFF: https://github.com/llvm/llvm-project/commit/dca7b11a326f523a93268dd17e969d1c26bcf40e.diff
LOG: [X86] Add tests showing failure to reduce the vector width of vpmaddwd/vpmaddubsw/pmulhrsw nodes (#180728)
Missing demanded elts handling
Added:
llvm/test/CodeGen/X86/vector-target-demanded-elts.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/vector-target-demanded-elts.ll b/llvm/test/CodeGen/X86/vector-target-demanded-elts.ll
new file mode 100644
index 0000000000000..84dbb03f5e292
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-target-demanded-elts.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
+
+define <4 x i32> @demanded_low_pmaddwd256_128(<16 x i16> %a0, <16 x i16> %a1) {
+; CHECK-LABEL: demanded_low_pmaddwd256_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %res = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a0, <16 x i16> %a1)
+ %ext = shufflevector <8 x i32> %res, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %ext
+}
+
+define <8 x i32> @demanded_low_pmaddwd512_256(<32 x i16> %x0, <32 x i16> %x1) {
+; CHECK-LABEL: demanded_low_pmaddwd512_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmaddwd %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
+; CHECK-NEXT: retq
+ %res = call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %x0, <32 x i16> %x1)
+ %ext = shufflevector <16 x i32> %res, <16 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i32> %ext
+}
+
+define <8 x i16> @demanded_low_pmaddubs256_128(<32 x i8> %a0, <32 x i8> %a1) {
+; CHECK-LABEL: demanded_low_pmaddubs256_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1)
+ %ext = shufflevector <16 x i16> %res, <16 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %ext
+}
+
+define <16 x i16> @demanded_low_pmaddubs512_256(<64 x i8> %x0, <64 x i8> %x1) {
+; CHECK-LABEL: demanded_low_pmaddubs512_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
+; CHECK-NEXT: retq
+ %res = call <32 x i16> @llvm.x86.avx512.pmaddubs.w.512(<64 x i8> %x0, <64 x i8> %x1)
+ %ext = shufflevector <32 x i16> %res, <32 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i16> %ext
+}
+
+define <8 x i16> @demanded_low_pmulhrsw256_128(<16 x i16> %a0, <16 x i16> %a1) {
+; CHECK-LABEL: demanded_low_pmulhrsw256_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %res = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> %a0, <16 x i16> %a1)
+ %ext = shufflevector <16 x i16> %res, <16 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %ext
+}
+
+define <16 x i16> @demanded_low_pmulhrsw512_256(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2) {
+; CHECK-LABEL: demanded_low_pmulhrsw512_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmulhrsw %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
+; CHECK-NEXT: retq
+ %res = call <32 x i16> @llvm.x86.avx512.pmul.hr.sw.512(<32 x i16> %x0, <32 x i16> %x1)
+ %ext = shufflevector <32 x i16> %res, <32 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i16> %ext
+}
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