[llvm] 8c5f31b - [RISCV] Enable select optimization by default (#178394)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 10 00:19:07 PST 2026
Author: Pengcheng Wang
Date: 2026-02-10T16:19:01+08:00
New Revision: 8c5f31b365dfc5ad9e8aa5756159961421a2eae3
URL: https://github.com/llvm/llvm-project/commit/8c5f31b365dfc5ad9e8aa5756159961421a2eae3
DIFF: https://github.com/llvm/llvm-project/commit/8c5f31b365dfc5ad9e8aa5756159961421a2eae3.diff
LOG: [RISCV] Enable select optimization by default (#178394)
And we add `TuneEnableSelectOptimize` to:
* `generic`
* `generic-ooo`
* `sifive-p550`
* `spacemit-x60`
Added:
Modified:
llvm/lib/Target/RISCV/RISCVProcessors.td
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
llvm/test/CodeGen/RISCV/selectopt.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index ca291052466be..af66c960a3ab8 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -89,7 +89,8 @@ class RISCVTuneProcessorModel<string n, SchedMachineModel m,
list<RISCVTuneFeature> ConfigurableTuneFeatures = [];
}
-defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
+defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore,
+ TuneEnableSelectOptimize];
def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
NoSchedModel,
@@ -425,6 +426,7 @@ def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
TuneVXRMPipelineFlush])>;
defvar SiFiveP500TuneFeatures = [TuneNoDefaultUnroll,
+ TuneEnableSelectOptimize,
TuneConditionalCompressedMoveFusion,
TuneLUIADDIFusion,
TuneAUIPCADDIFusion,
@@ -768,6 +770,7 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
TuneOptimizedNF2SegmentLoadStore,
TuneOptimizedNF3SegmentLoadStore,
TuneOptimizedNF4SegmentLoadStore,
+ TuneEnableSelectOptimize,
TuneVXRMPipelineFlush]> {
let MVendorID = 0x710;
let MArchID = 0x8000000058000001;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index fe4e0b6cfaebd..523507cd174f3 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -112,7 +112,7 @@ static cl::opt<bool> EnableCFIInstrInserter(
static cl::opt<bool>
EnableSelectOpt("riscv-select-opt", cl::Hidden,
cl::desc("Enable select to branch optimizations"),
- cl::init(false));
+ cl::init(true));
extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index d8dd000e1833b..c48e3859850cc 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -72,6 +72,15 @@
; CHECK-NEXT: Scalarize Masked Memory Intrinsics
; CHECK-NEXT: Expand reduction intrinsics
; CHECK-NEXT: Natural Loop Information
+; CHECK-NEXT: Post-Dominator Tree Construction
+; CHECK-NEXT: Branch Probability Analysis
+; CHECK-NEXT: Block Frequency Analysis
+; CHECK-NEXT: Lazy Branch Probability Analysis
+; CHECK-NEXT: Lazy Block Frequency Analysis
+; CHECK-NEXT: Optimization Remark Emitter
+; CHECK-NEXT: Optimize selects
+; CHECK-NEXT: Dominator Tree Construction
+; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Type Promotion
; CHECK-NEXT: CodeGen Prepare
; CHECK-NEXT: Dominator Tree Construction
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll b/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
index 8534ad379ebab..7f5933f0bb2b6 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
@@ -197,7 +197,7 @@ define void @amomax_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: mv s2, a1
; RV32-NEXT: j .LBB11_2
-; RV32-NEXT: .LBB11_1: # %atomicrmw.start
+; RV32-NEXT: .LBB11_1: # %select.end
; RV32-NEXT: # in Loop: Header=BB11_2 Depth=1
; RV32-NEXT: sw a4, 8(sp)
; RV32-NEXT: sw a5, 12(sp)
@@ -224,7 +224,7 @@ define void @amomax_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: bnez a0, .LBB11_1
-; RV32-NEXT: .LBB11_5: # %atomicrmw.start
+; RV32-NEXT: .LBB11_5: # %select.false
; RV32-NEXT: # in Loop: Header=BB11_2 Depth=1
; RV32-NEXT: mv a2, s2
; RV32-NEXT: mv a3, s0
@@ -273,7 +273,7 @@ define void @amomaxu_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: mv s2, a1
; RV32-NEXT: j .LBB13_2
-; RV32-NEXT: .LBB13_1: # %atomicrmw.start
+; RV32-NEXT: .LBB13_1: # %select.end
; RV32-NEXT: # in Loop: Header=BB13_2 Depth=1
; RV32-NEXT: sw a4, 8(sp)
; RV32-NEXT: sw a5, 12(sp)
@@ -300,7 +300,7 @@ define void @amomaxu_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: bnez a0, .LBB13_1
-; RV32-NEXT: .LBB13_5: # %atomicrmw.start
+; RV32-NEXT: .LBB13_5: # %select.false
; RV32-NEXT: # in Loop: Header=BB13_2 Depth=1
; RV32-NEXT: mv a2, s2
; RV32-NEXT: mv a3, s0
@@ -349,7 +349,7 @@ define void @amomin_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: mv s2, a1
; RV32-NEXT: j .LBB15_2
-; RV32-NEXT: .LBB15_1: # %atomicrmw.start
+; RV32-NEXT: .LBB15_1: # %select.end
; RV32-NEXT: # in Loop: Header=BB15_2 Depth=1
; RV32-NEXT: sw a4, 8(sp)
; RV32-NEXT: sw a5, 12(sp)
@@ -376,7 +376,7 @@ define void @amomin_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: beqz a0, .LBB15_1
-; RV32-NEXT: .LBB15_5: # %atomicrmw.start
+; RV32-NEXT: .LBB15_5: # %select.false
; RV32-NEXT: # in Loop: Header=BB15_2 Depth=1
; RV32-NEXT: mv a2, s2
; RV32-NEXT: mv a3, s0
@@ -425,7 +425,7 @@ define void @amominu_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: mv s2, a1
; RV32-NEXT: j .LBB17_2
-; RV32-NEXT: .LBB17_1: # %atomicrmw.start
+; RV32-NEXT: .LBB17_1: # %select.end
; RV32-NEXT: # in Loop: Header=BB17_2 Depth=1
; RV32-NEXT: sw a4, 8(sp)
; RV32-NEXT: sw a5, 12(sp)
@@ -452,7 +452,7 @@ define void @amominu_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: beqz a0, .LBB17_1
-; RV32-NEXT: .LBB17_5: # %atomicrmw.start
+; RV32-NEXT: .LBB17_5: # %select.false
; RV32-NEXT: # in Loop: Header=BB17_2 Depth=1
; RV32-NEXT: mv a2, s2
; RV32-NEXT: mv a3, s0
diff --git a/llvm/test/CodeGen/RISCV/selectopt.ll b/llvm/test/CodeGen/RISCV/selectopt.ll
index e82037bb59e20..9c2a79e8e04f8 100644
--- a/llvm/test/CodeGen/RISCV/selectopt.ll
+++ b/llvm/test/CodeGen/RISCV/selectopt.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \
-; RUN: -mtriple=riscv64 -S < %s \
+; RUN: -mtriple=riscv64 -mattr=-enable-select-opt -S < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,NO-SELECT-OPT
; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \
; RUN: -mtriple=riscv64 -mattr=+enable-select-opt -S < %s \
@@ -8,6 +8,12 @@
; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \
; RUN: -mtriple=riscv64 -mattr=+enable-select-opt,+predictable-select-expensive -S < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,SELECT-OPT,SELECT-OPT-EXPENSIVE
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \
+; RUN: -mtriple=riscv64 -mcpu=spacemit-x60 -S < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,SELECT-OPT,SELECT-OPT-NOT-EXPENSIVE,SPACEMIT-X60
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \
+; RUN: -mtriple=riscv64 -mcpu=sifive-p550 -S < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,SELECT-OPT,SELECT-OPT-NOT-EXPENSIVE,SIFIVE-P550
%struct.st = type { i32, i64, ptr, ptr, i16, ptr, ptr, i64, i64 }
@@ -875,9 +881,9 @@ define void @outer_latch_heuristic(ptr %dst, ptr %src, i64 %p, i64 %dim) {
; SELECT-OPT-NEXT: entry:
; SELECT-OPT-NEXT: br label [[OUTER_LOOP:%.*]]
; SELECT-OPT: outer.loop:
-; SELECT-OPT-NEXT: [[K_020_US:%.*]] = phi i64 [ [[INC7_US:%.*]], [[LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
-; SELECT-OPT-NEXT: [[J:%.*]] = phi i64 [ [[J_NEXT:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ]
-; SELECT-OPT-NEXT: [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ]
+; SELECT-OPT-NEXT: [[K_020_US:%.*]] = phi i64 [ [[INC7_US:%.*]], [[SELECT_END:%.*]] ], [ 0, [[ENTRY:%.*]] ]
+; SELECT-OPT-NEXT: [[J:%.*]] = phi i64 [ [[J_NEXT:%.*]], [[SELECT_END]] ], [ 0, [[ENTRY]] ]
+; SELECT-OPT-NEXT: [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], [[SELECT_END]] ], [ 0, [[ENTRY]] ]
; SELECT-OPT-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
; SELECT-OPT-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX_US]], align 8
; SELECT-OPT-NEXT: [[ARRAYIDX1_US:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
@@ -889,7 +895,7 @@ define void @outer_latch_heuristic(ptr %dst, ptr %src, i64 %p, i64 %dim) {
; SELECT-OPT-NEXT: [[CALL_I_US]] = tail call i64 @payload(i64 [[DIFF_04_I_US]], ptr [[TMP0]], ptr [[TMP1]], i64 [[P:%.*]])
; SELECT-OPT-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1
; SELECT-OPT-NEXT: [[EXITCOND_NOT_I_US:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0
-; SELECT-OPT-NEXT: br i1 [[EXITCOND_NOT_I_US]], label [[LATCH1:%.*]], label [[INNER_LOOP]]
+; SELECT-OPT-NEXT: br i1 [[EXITCOND_NOT_I_US]], label [[LATCH:%.*]], label [[INNER_LOOP]]
; SELECT-OPT: latch:
; SELECT-OPT-NEXT: [[CMP2_US:%.*]] = icmp sgt i64 [[CALL_I_US]], -1
; SELECT-OPT-NEXT: [[DIFF_0_LCSSA_I_LOBIT_US:%.*]] = lshr i64 [[CALL_I_US]], 63
@@ -897,10 +903,10 @@ define void @outer_latch_heuristic(ptr %dst, ptr %src, i64 %p, i64 %dim) {
; SELECT-OPT-NEXT: br i1 [[CMP2_US_FROZEN]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_FALSE_SINK:%.*]]
; SELECT-OPT: select.true.sink:
; SELECT-OPT-NEXT: [[TMP2:%.*]] = add nsw i64 [[J]], 1
-; SELECT-OPT-NEXT: br label [[LATCH]]
+; SELECT-OPT-NEXT: br label [[SELECT_END]]
; SELECT-OPT: select.false.sink:
; SELECT-OPT-NEXT: [[TMP3:%.*]] = add nsw i64 1, [[I]]
-; SELECT-OPT-NEXT: br label [[LATCH]]
+; SELECT-OPT-NEXT: br label [[SELECT_END]]
; SELECT-OPT: select.end:
; SELECT-OPT-NEXT: [[I_NEXT]] = phi i64 [ [[I]], [[SELECT_TRUE_SINK]] ], [ [[TMP3]], [[SELECT_FALSE_SINK]] ]
; SELECT-OPT-NEXT: [[J_NEXT]] = phi i64 [ [[TMP2]], [[SELECT_TRUE_SINK]] ], [ [[J]], [[SELECT_FALSE_SINK]] ]
@@ -956,3 +962,5 @@ exit:
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; SELECT-OPT-EXPENSIVE: {{.*}}
; SELECT-OPT-NOT-EXPENSIVE: {{.*}}
+; SIFIVE-P550: {{.*}}
+; SPACEMIT-X60: {{.*}}
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