[llvm] [Hexagon] Add support for V128i1/V64i1/V32i1 predicate store/load in HVX (PR #180701)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/Hexagon/HexagonISelLowering.h llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 9d7c63ac9..4e879f47d 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -3666,8 +3666,10 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
     case ISD::MLOAD:
     case ISD::MSTORE:                  return LowerHvxMaskedOp(Op, DAG);
     // Unaligned loads will be handled by the default lowering.
-    case ISD::LOAD:                    return LowerHvxLoad(Op, DAG);
-    case ISD::STORE:                   return LowerHvxStore(Op, DAG);
+    case ISD::LOAD:
+      return LowerHvxLoad(Op, DAG);
+    case ISD::STORE:
+      return LowerHvxStore(Op, DAG);
     case ISD::FP_EXTEND:               return LowerHvxFpExtend(Op, DAG);
     case ISD::FP_TO_SINT:
     case ISD::FP_TO_UINT:              return LowerHvxFpToInt(Op, DAG);

``````````

</details>


https://github.com/llvm/llvm-project/pull/180701