[llvm] [RISCV] Stash GPR to FPR if emergency spill slot is not reachable (PR #180685)

[via llvm-commits]

================
@@ -566,8 +569,25 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   }
 
   if (Offset.getScalable() || Offset.getFixed()) {
-    Register DestReg;
-    if (MI.getOpcode() == RISCV::ADDI)
+    bool ScavengingFailed =
+        RS && RS->getRegsAvailable(&RISCV::GPRRegClass).none();
+    const TargetRegisterClass *FPR64 = &RISCV::FPR64RegClass;
+    bool CanDoFPR64Move = ST.is64Bit() && ST.hasStdExtD() && RS &&
+                          RS->getRegsAvailable(FPR64).any();
+    bool IsLoadStore =
+        (MI.getOpcode() == RISCV::LD || MI.getOpcode() == RISCV::SD);
+    bool DoFPR64Move = ScavengingFailed && CanDoFPR64Move && IsLoadStore;
+    Register DestReg, FPRReg;
+
+    // The register scavenger is unable to get a GPR but can get a FPR. We
+    // need to stash a GPR into a FPR so that we can free one up.
+    if (DoFPR64Move) {
----------------
LukeZhuang wrote:

There is another DoFPR64Move below, so I extract them out.

https://github.com/llvm/llvm-project/pull/180685