[llvm] [NVPTX] Scalarize v2f32 instructions if input operand guarantees need for register coalescing (PR #180113)

[via llvm-commits]

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@@ -6133,14 +6137,120 @@ static SDValue PerformADDCombine(SDNode *N,
   return PerformADDCombineWithOperands(N, N1, N0, DCI);
 }
 
+/// Check if a v2f32 BUILD_VECTOR provably packs values from non-adjacent
+/// register pairs (non-coalescable).
+static bool isNonCoalescableBuildVector(SDValue BV) {
+  if (BV.getOpcode() != ISD::BUILD_VECTOR || BV.getValueType() != MVT::v2f32)
+    return false;
+
+  SDValue Elt0 = BV.getOperand(0);
+  SDValue Elt1 = BV.getOperand(1);
+
+  bool IsExt0 = Elt0.getOpcode() == ISD::EXTRACT_VECTOR_ELT;
+  bool IsExt1 = Elt1.getOpcode() == ISD::EXTRACT_VECTOR_ELT;
+
+  // If neither element is an EXTRACT_VECTOR_ELT they are free-standing
+  // scalars and the register allocator can still place them side-by-side.
+  if (!IsExt0 && !IsExt1)
+    return false;
+
+  // If exactly one element is an EXTRACT_VECTOR_ELT, the other is a scalar
+  // that cannot generally occupy the adjacent register slot.
+  if (IsExt0 != IsExt1)
+    return true;
+
+  // At this point both sources are extracting from vectors. If they are from
+  // different vectors, then the BUILD_VECTOR is non-coalescable.
+  SDValue Src0 = Elt0.getOperand(0);
+  SDValue Src1 = Elt1.getOperand(0);
+  if (Src0 != Src1)
+    return true;
+
+  // Even adjacent index pairs such as {0, 1} and {2, 3} are coalescable
+  auto *Idx0 = dyn_cast<ConstantSDNode>(Elt0.getOperand(1));
+  auto *Idx1 = dyn_cast<ConstantSDNode>(Elt1.getOperand(1));
+  if (!Idx0 || !Idx1)
+    return false;
----------------
modiking wrote:

Thinking through the cases:
1. If both are dynamic indices we'll get 2 loads + vector spill so the RA can place the registers adjacently.
2. If one is dynamic and one is static we'll have a load + a extract. However, the static result will need an additional register next to the dynamic one which requires additional register/instructions.
3. If both are static we check for adjacency.

So (1) is coalescable but (2) isn't and (3) is the case that's already checked.

https://github.com/llvm/llvm-project/pull/180113