[llvm] f33ea53 - [RISCV] Remove redundant czero in multi-word comparisons (#180485)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 9 21:48:19 PST 2026
Author: Craig Topper
Date: 2026-02-09T21:48:14-08:00
New Revision: f33ea53451f01bd82cbe7bc7f795f5b4ba731f2b
URL: https://github.com/llvm/llvm-project/commit/f33ea53451f01bd82cbe7bc7f795f5b4ba731f2b
DIFF: https://github.com/llvm/llvm-project/commit/f33ea53451f01bd82cbe7bc7f795f5b4ba731f2b.diff
LOG: [RISCV] Remove redundant czero in multi-word comparisons (#180485)
When comparing multi-word integers with Zicond, we generate:
(or (czero_eqz (lo1 < lo2), (hi1 == hi2)),
(czero_nez (hi1 < hi2), (hi1 == hi2)))
The czero_nez is redundant because when hi1 == hi2 is true, hi1 < hi2 is
already 0. This patch adds a DAG combine to recognize:
czero_nez (setcc X, Y, CC), (setcc X, Y, eq) -> (setcc X, Y, CC)
when CC is a strict inequality (lt, gt, ult, ugt).
This saves one instruction in 128-bit comparisons on RV64 with Zicond.
Note the czero_nez becomes a czero.eqz in the final assembly because the
seteq is replaced by an xor that produces 0 when the values are equal.
Part of #179584
Assisted-by: claude
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/condops.ll
llvm/test/CodeGen/RISCV/xaluo.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c30d585bf89dc..430946ebc2411 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21530,6 +21530,23 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return DAG.getNode(CCVal == ISD::SETNE ? Opc : InvOpc, SDLoc(N),
N->getValueType(0), Val, Cond.getOperand(0));
}
+
+ // czero_nez (setcc X, Y, CC), (setcc X, Y, eq) -> (setcc X, Y, CC)
+ // if CC is a strict inequality (lt, gt, ult, ugt), because when X == Y
+ // the setcc result is already 0. The eq operands can be in either order.
+ if (Opc == RISCVISD::CZERO_NEZ && Val.getOpcode() == ISD::SETCC &&
+ Cond.getOpcode() == ISD::SETCC &&
+ cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ) {
+ ISD::CondCode ValCC = cast<CondCodeSDNode>(Val.getOperand(2))->get();
+ bool SameOperands = (Val.getOperand(0) == Cond.getOperand(0) &&
+ Val.getOperand(1) == Cond.getOperand(1)) ||
+ (Val.getOperand(0) == Cond.getOperand(1) &&
+ Val.getOperand(1) == Cond.getOperand(0));
+ if (SameOperands && (ValCC == ISD::SETLT || ValCC == ISD::SETGT ||
+ ValCC == ISD::SETULT || ValCC == ISD::SETUGT))
+ return Val;
+ }
+
return SDValue();
}
case RISCVISD::SELECT_CC: {
diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll
index 9d95f1f5c9615..389a8394e3c25 100644
--- a/llvm/test/CodeGen/RISCV/condops.ll
+++ b/llvm/test/CodeGen/RISCV/condops.ll
@@ -1526,9 +1526,8 @@ define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32XVENTANACONDOPS-LABEL: setgt:
; RV32XVENTANACONDOPS: # %bb.0:
; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
-; RV32XVENTANACONDOPS-NEXT: slt a1, a3, a1
; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0
-; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: slt a1, a3, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0
@@ -1557,9 +1556,8 @@ define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32ZICOND-LABEL: setgt:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3
-; RV32ZICOND-NEXT: slt a1, a3, a1
; RV32ZICOND-NEXT: sltu a0, a2, a0
-; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT: slt a1, a3, a1
; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: czero.nez a1, a6, a0
@@ -1613,9 +1611,8 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32XVENTANACONDOPS-LABEL: setge:
; RV32XVENTANACONDOPS: # %bb.0:
; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
-; RV32XVENTANACONDOPS-NEXT: slt a1, a1, a3
; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2
-; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: slt a1, a1, a3
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0
@@ -1644,9 +1641,8 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32ZICOND-LABEL: setge:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3
-; RV32ZICOND-NEXT: slt a1, a1, a3
; RV32ZICOND-NEXT: sltu a0, a0, a2
-; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT: slt a1, a1, a3
; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: czero.eqz a1, a6, a0
@@ -1700,9 +1696,8 @@ define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32XVENTANACONDOPS-LABEL: setlt:
; RV32XVENTANACONDOPS: # %bb.0:
; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
-; RV32XVENTANACONDOPS-NEXT: slt a1, a1, a3
; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2
-; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: slt a1, a1, a3
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0
@@ -1731,9 +1726,8 @@ define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32ZICOND-LABEL: setlt:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3
-; RV32ZICOND-NEXT: slt a1, a1, a3
; RV32ZICOND-NEXT: sltu a0, a0, a2
-; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT: slt a1, a1, a3
; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: czero.nez a1, a6, a0
@@ -1787,9 +1781,8 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32XVENTANACONDOPS-LABEL: setle:
; RV32XVENTANACONDOPS: # %bb.0:
; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
-; RV32XVENTANACONDOPS-NEXT: slt a1, a3, a1
; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0
-; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: slt a1, a3, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0
@@ -1818,9 +1811,8 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32ZICOND-LABEL: setle:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3
-; RV32ZICOND-NEXT: slt a1, a3, a1
; RV32ZICOND-NEXT: sltu a0, a2, a0
-; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT: slt a1, a3, a1
; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: czero.eqz a1, a6, a0
@@ -1874,9 +1866,8 @@ define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32XVENTANACONDOPS-LABEL: setugt:
; RV32XVENTANACONDOPS: # %bb.0:
; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
-; RV32XVENTANACONDOPS-NEXT: sltu a1, a3, a1
; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0
-; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a3, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0
@@ -1905,9 +1896,8 @@ define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32ZICOND-LABEL: setugt:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3
-; RV32ZICOND-NEXT: sltu a1, a3, a1
; RV32ZICOND-NEXT: sltu a0, a2, a0
-; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT: sltu a1, a3, a1
; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: czero.nez a1, a6, a0
@@ -1961,9 +1951,8 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32XVENTANACONDOPS-LABEL: setuge:
; RV32XVENTANACONDOPS: # %bb.0:
; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
-; RV32XVENTANACONDOPS-NEXT: sltu a1, a1, a3
; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2
-; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a1, a3
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0
@@ -1992,9 +1981,8 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32ZICOND-LABEL: setuge:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3
-; RV32ZICOND-NEXT: sltu a1, a1, a3
; RV32ZICOND-NEXT: sltu a0, a0, a2
-; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT: sltu a1, a1, a3
; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: czero.eqz a1, a6, a0
@@ -2048,9 +2036,8 @@ define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32XVENTANACONDOPS-LABEL: setult:
; RV32XVENTANACONDOPS: # %bb.0:
; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
-; RV32XVENTANACONDOPS-NEXT: sltu a1, a1, a3
; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2
-; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a1, a3
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0
@@ -2079,9 +2066,8 @@ define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32ZICOND-LABEL: setult:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3
-; RV32ZICOND-NEXT: sltu a1, a1, a3
; RV32ZICOND-NEXT: sltu a0, a0, a2
-; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT: sltu a1, a1, a3
; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: czero.nez a1, a6, a0
@@ -2135,9 +2121,8 @@ define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32XVENTANACONDOPS-LABEL: setule:
; RV32XVENTANACONDOPS: # %bb.0:
; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
-; RV32XVENTANACONDOPS-NEXT: sltu a1, a3, a1
; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0
-; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a3, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0
@@ -2166,9 +2151,8 @@ define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32ZICOND-LABEL: setule:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3
-; RV32ZICOND-NEXT: sltu a1, a3, a1
; RV32ZICOND-NEXT: sltu a0, a2, a0
-; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT: sltu a1, a3, a1
; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: czero.eqz a1, a6, a0
diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll
index 62f08d7831dda..d314634242f29 100644
--- a/llvm/test/CodeGen/RISCV/xaluo.ll
+++ b/llvm/test/CodeGen/RISCV/xaluo.ll
@@ -660,11 +660,10 @@ define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, ptr %res) {
; RV32ZICOND-NEXT: add a2, a0, a2
; RV32ZICOND-NEXT: sltu a0, a2, a0
; RV32ZICOND-NEXT: add a3, a3, a0
-; RV32ZICOND-NEXT: xor a5, a3, a1
-; RV32ZICOND-NEXT: sltu a1, a3, a1
-; RV32ZICOND-NEXT: czero.eqz a1, a1, a5
-; RV32ZICOND-NEXT: czero.nez a0, a0, a5
-; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: sltu a5, a3, a1
+; RV32ZICOND-NEXT: xor a1, a3, a1
+; RV32ZICOND-NEXT: czero.nez a0, a0, a1
+; RV32ZICOND-NEXT: or a0, a0, a5
; RV32ZICOND-NEXT: sw a2, 0(a4)
; RV32ZICOND-NEXT: sw a3, 4(a4)
; RV32ZICOND-NEXT: ret
@@ -1152,11 +1151,10 @@ define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, ptr %res) {
; RV32ZICOND-NEXT: sub a2, a0, a2
; RV32ZICOND-NEXT: sub a3, a3, a5
; RV32ZICOND-NEXT: sltu a0, a0, a2
-; RV32ZICOND-NEXT: xor a5, a3, a1
-; RV32ZICOND-NEXT: sltu a1, a1, a3
-; RV32ZICOND-NEXT: czero.eqz a1, a1, a5
-; RV32ZICOND-NEXT: czero.nez a0, a0, a5
-; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: sltu a5, a1, a3
+; RV32ZICOND-NEXT: xor a1, a3, a1
+; RV32ZICOND-NEXT: czero.nez a0, a0, a1
+; RV32ZICOND-NEXT: or a0, a0, a5
; RV32ZICOND-NEXT: sw a2, 0(a4)
; RV32ZICOND-NEXT: sw a3, 4(a4)
; RV32ZICOND-NEXT: ret
@@ -2426,11 +2424,10 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
; RV32ZICOND-NEXT: add a5, a0, a2
; RV32ZICOND-NEXT: sltu a5, a5, a0
; RV32ZICOND-NEXT: add a4, a4, a5
-; RV32ZICOND-NEXT: xor a6, a4, a1
-; RV32ZICOND-NEXT: sltu a4, a4, a1
-; RV32ZICOND-NEXT: czero.eqz a4, a4, a6
-; RV32ZICOND-NEXT: czero.nez a5, a5, a6
-; RV32ZICOND-NEXT: or a4, a5, a4
+; RV32ZICOND-NEXT: sltu a6, a4, a1
+; RV32ZICOND-NEXT: xor a4, a4, a1
+; RV32ZICOND-NEXT: czero.nez a4, a5, a4
+; RV32ZICOND-NEXT: or a4, a4, a6
; RV32ZICOND-NEXT: czero.nez a2, a2, a4
; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
; RV32ZICOND-NEXT: czero.nez a3, a3, a4
@@ -2501,11 +2498,10 @@ define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
; RV32ZICOND-NEXT: add a2, a0, a2
; RV32ZICOND-NEXT: sltu a0, a2, a0
; RV32ZICOND-NEXT: add a3, a3, a0
-; RV32ZICOND-NEXT: xor a2, a3, a1
-; RV32ZICOND-NEXT: sltu a1, a3, a1
-; RV32ZICOND-NEXT: czero.eqz a1, a1, a2
-; RV32ZICOND-NEXT: czero.nez a0, a0, a2
-; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: sltu a2, a3, a1
+; RV32ZICOND-NEXT: xor a1, a3, a1
+; RV32ZICOND-NEXT: czero.nez a0, a0, a1
+; RV32ZICOND-NEXT: or a0, a0, a2
; RV32ZICOND-NEXT: xori a0, a0, 1
; RV32ZICOND-NEXT: ret
;
@@ -2983,11 +2979,10 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
; RV32ZICOND-NEXT: sub a6, a0, a2
; RV32ZICOND-NEXT: sub a5, a5, a4
; RV32ZICOND-NEXT: sltu a4, a0, a6
-; RV32ZICOND-NEXT: xor a6, a5, a1
-; RV32ZICOND-NEXT: sltu a5, a1, a5
-; RV32ZICOND-NEXT: czero.eqz a5, a5, a6
-; RV32ZICOND-NEXT: czero.nez a4, a4, a6
-; RV32ZICOND-NEXT: or a4, a4, a5
+; RV32ZICOND-NEXT: sltu a6, a1, a5
+; RV32ZICOND-NEXT: xor a5, a5, a1
+; RV32ZICOND-NEXT: czero.nez a4, a4, a5
+; RV32ZICOND-NEXT: or a4, a4, a6
; RV32ZICOND-NEXT: czero.nez a2, a2, a4
; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
; RV32ZICOND-NEXT: czero.nez a3, a3, a4
@@ -3064,12 +3059,11 @@ define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
; RV32ZICOND-NEXT: sub a3, a1, a3
; RV32ZICOND-NEXT: sub a2, a0, a2
; RV32ZICOND-NEXT: sub a3, a3, a4
+; RV32ZICOND-NEXT: sltu a4, a1, a3
+; RV32ZICOND-NEXT: xor a1, a3, a1
; RV32ZICOND-NEXT: sltu a0, a0, a2
-; RV32ZICOND-NEXT: xor a2, a3, a1
-; RV32ZICOND-NEXT: sltu a1, a1, a3
-; RV32ZICOND-NEXT: czero.eqz a1, a1, a2
-; RV32ZICOND-NEXT: czero.nez a0, a0, a2
-; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: czero.nez a0, a0, a1
+; RV32ZICOND-NEXT: or a0, a0, a4
; RV32ZICOND-NEXT: xori a0, a0, 1
; RV32ZICOND-NEXT: ret
;
@@ -4152,11 +4146,10 @@ define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
; RV32ZICOND-NEXT: add a2, a0, a2
; RV32ZICOND-NEXT: sltu a0, a2, a0
; RV32ZICOND-NEXT: add a3, a3, a0
-; RV32ZICOND-NEXT: xor a2, a3, a1
-; RV32ZICOND-NEXT: sltu a1, a3, a1
-; RV32ZICOND-NEXT: czero.eqz a1, a1, a2
-; RV32ZICOND-NEXT: czero.nez a0, a0, a2
-; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: sltu a2, a3, a1
+; RV32ZICOND-NEXT: xor a1, a3, a1
+; RV32ZICOND-NEXT: czero.nez a0, a0, a1
+; RV32ZICOND-NEXT: or a0, a0, a2
; RV32ZICOND-NEXT: beqz a0, .LBB55_2
; RV32ZICOND-NEXT: # %bb.1: # %overflow
; RV32ZICOND-NEXT: li a0, 0
@@ -4524,12 +4517,11 @@ define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
; RV32ZICOND-NEXT: sub a3, a1, a3
; RV32ZICOND-NEXT: sub a2, a0, a2
; RV32ZICOND-NEXT: sub a3, a3, a4
+; RV32ZICOND-NEXT: sltu a4, a1, a3
+; RV32ZICOND-NEXT: xor a1, a3, a1
; RV32ZICOND-NEXT: sltu a0, a0, a2
-; RV32ZICOND-NEXT: xor a2, a3, a1
-; RV32ZICOND-NEXT: sltu a1, a1, a3
-; RV32ZICOND-NEXT: czero.eqz a1, a1, a2
-; RV32ZICOND-NEXT: czero.nez a0, a0, a2
-; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: czero.nez a0, a0, a1
+; RV32ZICOND-NEXT: or a0, a0, a4
; RV32ZICOND-NEXT: beqz a0, .LBB59_2
; RV32ZICOND-NEXT: # %bb.1: # %overflow
; RV32ZICOND-NEXT: li a0, 0
@@ -5261,9 +5253,8 @@ define zeroext i1 @umulo2.br.i64(i64 %v1) {
; RV32ZICOND-NEXT: sltu a0, a2, a0
; RV32ZICOND-NEXT: add a3, a3, a0
; RV32ZICOND-NEXT: xor a2, a3, a1
-; RV32ZICOND-NEXT: sltu a1, a3, a1
-; RV32ZICOND-NEXT: czero.eqz a1, a1, a2
; RV32ZICOND-NEXT: czero.nez a0, a0, a2
+; RV32ZICOND-NEXT: sltu a1, a3, a1
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: beqz a0, .LBB65_2
; RV32ZICOND-NEXT: # %bb.1: # %overflow
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