[llvm] [RISCV] Use ADDD for GPR Pair Move with P (PR #180671)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 14e85d9db..f59675549 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -544,8 +544,8 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       if (STI.hasStdExtP()) {
         // On RV32P, `addd` is a GPR Pair Add
         BuildMI(MBB, MBBI, DL, get(RISCV::ADDD), DstReg)
-          .addReg(SrcReg, KillFlag | getRenamableRegState(RenamableSrc))
-          .addReg(RISCV::X0_Pair);
+            .addReg(SrcReg, KillFlag | getRenamableRegState(RenamableSrc))
+            .addReg(RISCV::X0_Pair);
         return;
       }
     }

``````````

</details>


https://github.com/llvm/llvm-project/pull/180671