[llvm] [AMDGPU][SIInsertWaitcnts][NFC] Drop `AMDGPU::` (PR #180663)
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llvm-commits at lists.llvm.org
Mon Feb 9 17:57:10 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: vporpo (vporpo)
<details>
<summary>Changes</summary>
A prior patch introduced `using namespace llvm::AMDGPU`, so this patch drops `AMDGPU::`.
---
Patch is 59.31 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/180663.diff
1 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp (+230-265)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 7dfe0da7ef81a..58fc2c5884caa 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -71,7 +71,7 @@ static cl::opt<bool> ExpertSchedulingModeFlag(
namespace {
// Get the maximum wait count value for a given counter type.
-static unsigned getWaitCountMax(const AMDGPU::HardwareLimits &Limits,
+static unsigned getWaitCountMax(const HardwareLimits &Limits,
InstCounterType T) {
switch (T) {
case LOAD_CNT:
@@ -100,7 +100,7 @@ static unsigned getWaitCountMax(const AMDGPU::HardwareLimits &Limits,
}
static bool isSoftXcnt(MachineInstr &MI) {
- return MI.getOpcode() == AMDGPU::S_WAIT_XCNT_soft;
+ return MI.getOpcode() == S_WAIT_XCNT_soft;
}
static bool isAtomicRMW(MachineInstr &MI) {
@@ -230,9 +230,8 @@ enum VmemType {
// counter. Only used if GCNSubtarget::hasExtendedWaitCounts()
// returns true, and does not cover VA_VDST or VM_VSRC.
static const unsigned instrsForExtendedCounterTypes[NUM_EXTENDED_INST_CNTS] = {
- AMDGPU::S_WAIT_LOADCNT, AMDGPU::S_WAIT_DSCNT, AMDGPU::S_WAIT_EXPCNT,
- AMDGPU::S_WAIT_STORECNT, AMDGPU::S_WAIT_SAMPLECNT, AMDGPU::S_WAIT_BVHCNT,
- AMDGPU::S_WAIT_KMCNT, AMDGPU::S_WAIT_XCNT};
+ S_WAIT_LOADCNT, S_WAIT_DSCNT, S_WAIT_EXPCNT, S_WAIT_STORECNT,
+ S_WAIT_SAMPLECNT, S_WAIT_BVHCNT, S_WAIT_KMCNT, S_WAIT_XCNT};
static bool updateVMCntOnly(const MachineInstr &Inst) {
return (SIInstrInfo::isVMEM(Inst) && !SIInstrInfo::isFLAT(Inst)) ||
@@ -249,9 +248,8 @@ VmemType getVmemType(const MachineInstr &Inst) {
assert(updateVMCntOnly(Inst));
if (!SIInstrInfo::isImage(Inst))
return VMEM_NOSAMPLER;
- const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Inst.getOpcode());
- const AMDGPU::MIMGBaseOpcodeInfo *BaseInfo =
- AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
+ const MIMGInfo *Info = getMIMGInfo(Inst.getOpcode());
+ const MIMGBaseOpcodeInfo *BaseInfo = getMIMGBaseOpcodeInfo(Info->BaseOpcode);
if (BaseInfo->BVH)
return VMEM_BVH;
@@ -265,11 +263,11 @@ VmemType getVmemType(const MachineInstr &Inst) {
return VMEM_NOSAMPLER;
}
-void addWait(AMDGPU::Waitcnt &Wait, InstCounterType T, unsigned Count) {
+void addWait(Waitcnt &Wait, InstCounterType T, unsigned Count) {
Wait.set(T, std::min(Wait.get(T), Count));
}
-void setNoWait(AMDGPU::Waitcnt &Wait, InstCounterType T) { Wait.set(T, ~0u); }
+void setNoWait(Waitcnt &Wait, InstCounterType T) { Wait.set(T, ~0u); }
/// A small set of events.
class WaitEventSet {
@@ -353,19 +351,19 @@ class WaitcntGenerator {
protected:
const GCNSubtarget &ST;
const SIInstrInfo &TII;
- AMDGPU::IsaVersion IV;
+ IsaVersion IV;
InstCounterType MaxCounter;
bool OptNone;
bool ExpandWaitcntProfiling = false;
- const AMDGPU::HardwareLimits *Limits = nullptr;
+ const HardwareLimits *Limits = nullptr;
public:
WaitcntGenerator() = delete;
WaitcntGenerator(const WaitcntGenerator &) = delete;
WaitcntGenerator(const MachineFunction &MF, InstCounterType MaxCounter,
- const AMDGPU::HardwareLimits *Limits)
+ const HardwareLimits *Limits)
: ST(MF.getSubtarget<GCNSubtarget>()), TII(*ST.getInstrInfo()),
- IV(AMDGPU::getIsaVersion(ST.getCPU())), MaxCounter(MaxCounter),
+ IV(getIsaVersion(ST.getCPU())), MaxCounter(MaxCounter),
OptNone(MF.getFunction().hasOptNone() ||
MF.getTarget().getOptLevel() == CodeGenOptLevel::None),
ExpandWaitcntProfiling(
@@ -376,7 +374,7 @@ class WaitcntGenerator {
// optimization.
bool isOptNone() const { return OptNone; }
- const AMDGPU::HardwareLimits &getLimits() const { return *Limits; }
+ const HardwareLimits &getLimits() const { return *Limits; }
// Edits an existing sequence of wait count instructions according
// to an incoming Waitcnt value, which is itself updated to reflect
@@ -391,7 +389,7 @@ class WaitcntGenerator {
// instructions later, as can happen on gfx12.
virtual bool
applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets,
- MachineInstr &OldWaitcntInstr, AMDGPU::Waitcnt &Wait,
+ MachineInstr &OldWaitcntInstr, Waitcnt &Wait,
MachineBasicBlock::instr_iterator It) const = 0;
// Transform a soft waitcnt into a normal one.
@@ -402,7 +400,7 @@ class WaitcntGenerator {
// ScoreBrackets is used for profiling expansion.
virtual bool createNewWaitcnt(MachineBasicBlock &Block,
MachineBasicBlock::instr_iterator It,
- AMDGPU::Waitcnt Wait,
+ Waitcnt Wait,
const WaitcntBrackets &ScoreBrackets) = 0;
// Returns the WaitEventSet that corresponds to counter \p T.
@@ -419,7 +417,7 @@ class WaitcntGenerator {
// Returns a new waitcnt with all counters except VScnt set to 0. If
// IncludeVSCnt is true, VScnt is set to 0, otherwise it is set to ~0u.
- virtual AMDGPU::Waitcnt getAllZeroWaitcnt(bool IncludeVSCnt) const = 0;
+ virtual Waitcnt getAllZeroWaitcnt(bool IncludeVSCnt) const = 0;
virtual ~WaitcntGenerator() = default;
};
@@ -444,19 +442,18 @@ class WaitcntGeneratorPreGFX12 final : public WaitcntGenerator {
using WaitcntGenerator::WaitcntGenerator;
bool
applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets,
- MachineInstr &OldWaitcntInstr, AMDGPU::Waitcnt &Wait,
+ MachineInstr &OldWaitcntInstr, Waitcnt &Wait,
MachineBasicBlock::instr_iterator It) const override;
bool createNewWaitcnt(MachineBasicBlock &Block,
- MachineBasicBlock::instr_iterator It,
- AMDGPU::Waitcnt Wait,
+ MachineBasicBlock::instr_iterator It, Waitcnt Wait,
const WaitcntBrackets &ScoreBrackets) override;
const WaitEventSet &getWaitEvents(InstCounterType T) const override {
return WaitEventMaskForInstPreGFX12[T];
}
- AMDGPU::Waitcnt getAllZeroWaitcnt(bool IncludeVSCnt) const override;
+ Waitcnt getAllZeroWaitcnt(bool IncludeVSCnt) const override;
};
class WaitcntGeneratorGFX12Plus final : public WaitcntGenerator {
@@ -481,25 +478,23 @@ class WaitcntGeneratorGFX12Plus final : public WaitcntGenerator {
WaitcntGeneratorGFX12Plus() = delete;
WaitcntGeneratorGFX12Plus(const MachineFunction &MF,
InstCounterType MaxCounter,
- const AMDGPU::HardwareLimits *Limits,
- bool IsExpertMode)
+ const HardwareLimits *Limits, bool IsExpertMode)
: WaitcntGenerator(MF, MaxCounter, Limits), IsExpertMode(IsExpertMode) {}
bool
applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets,
- MachineInstr &OldWaitcntInstr, AMDGPU::Waitcnt &Wait,
+ MachineInstr &OldWaitcntInstr, Waitcnt &Wait,
MachineBasicBlock::instr_iterator It) const override;
bool createNewWaitcnt(MachineBasicBlock &Block,
- MachineBasicBlock::instr_iterator It,
- AMDGPU::Waitcnt Wait,
+ MachineBasicBlock::instr_iterator It, Waitcnt Wait,
const WaitcntBrackets &ScoreBrackets) override;
const WaitEventSet &getWaitEvents(InstCounterType T) const override {
return WaitEventMaskForInstGFX12Plus[T];
}
- AMDGPU::Waitcnt getAllZeroWaitcnt(bool IncludeVSCnt) const override;
+ Waitcnt getAllZeroWaitcnt(bool IncludeVSCnt) const override;
};
// Flags indicating which counters should be flushed in a loop preheader.
@@ -545,7 +540,7 @@ class SIInsertWaitcnts {
// with insertion of DEALLOC_VGPRS messages.
DenseMap<MachineInstr *, bool> EndPgmInsts;
- AMDGPU::HardwareLimits Limits;
+ HardwareLimits Limits;
public:
SIInsertWaitcnts(MachineLoopInfo *MLI, MachinePostDominatorTree *PDT,
@@ -556,7 +551,7 @@ class SIInsertWaitcnts {
(void)ForceVMCounter;
}
- const AMDGPU::HardwareLimits &getLimits() const { return Limits; }
+ const HardwareLimits &getLimits() const { return Limits; }
PreheaderFlushFlags getPreheaderFlushFlags(MachineLoop *ML,
const WaitcntBrackets &Brackets);
@@ -608,11 +603,11 @@ class SIInsertWaitcnts {
WaitEventType getVmemWaitEventType(const MachineInstr &Inst) const {
switch (Inst.getOpcode()) {
// FIXME: GLOBAL_INV needs to be tracked with xcnt too.
- case AMDGPU::GLOBAL_INV:
+ case GLOBAL_INV:
return GLOBAL_INV_ACCESS; // tracked using loadcnt, but doesn't write
// VGPRs
- case AMDGPU::GLOBAL_WB:
- case AMDGPU::GLOBAL_WBINV:
+ case GLOBAL_WB:
+ case GLOBAL_WBINV:
return VMEM_WRITE_ACCESS; // tracked using storecnt
default:
break;
@@ -646,8 +641,7 @@ class SIInsertWaitcnts {
WaitcntBrackets &ScoreBrackets,
MachineInstr *OldWaitcntInstr,
PreheaderFlushFlags FlushFlags);
- bool generateWaitcnt(AMDGPU::Waitcnt Wait,
- MachineBasicBlock::instr_iterator It,
+ bool generateWaitcnt(Waitcnt Wait, MachineBasicBlock::instr_iterator It,
MachineBasicBlock &Block, WaitcntBrackets &ScoreBrackets,
MachineInstr *OldWaitcntInstr);
void updateEventWaitcntAfter(MachineInstr &Inst,
@@ -754,24 +748,19 @@ class WaitcntBrackets {
bool merge(const WaitcntBrackets &Other);
bool counterOutOfOrder(InstCounterType T) const;
- void simplifyWaitcnt(AMDGPU::Waitcnt &Wait) const {
- simplifyWaitcnt(Wait, Wait);
- }
- void simplifyWaitcnt(const AMDGPU::Waitcnt &CheckWait,
- AMDGPU::Waitcnt &UpdateWait) const;
+ void simplifyWaitcnt(Waitcnt &Wait) const { simplifyWaitcnt(Wait, Wait); }
+ void simplifyWaitcnt(const Waitcnt &CheckWait, Waitcnt &UpdateWait) const;
void simplifyWaitcnt(InstCounterType T, unsigned &Count) const;
- void simplifyXcnt(const AMDGPU::Waitcnt &CheckWait,
- AMDGPU::Waitcnt &UpdateWait) const;
- void simplifyVmVsrc(const AMDGPU::Waitcnt &CheckWait,
- AMDGPU::Waitcnt &UpdateWait) const;
+ void simplifyXcnt(const Waitcnt &CheckWait, Waitcnt &UpdateWait) const;
+ void simplifyVmVsrc(const Waitcnt &CheckWait, Waitcnt &UpdateWait) const;
void determineWaitForPhysReg(InstCounterType T, MCPhysReg Reg,
- AMDGPU::Waitcnt &Wait) const;
+ Waitcnt &Wait) const;
void determineWaitForLDSDMA(InstCounterType T, VMEMID TID,
- AMDGPU::Waitcnt &Wait) const;
+ Waitcnt &Wait) const;
void tryClearSCCWriteEvent(MachineInstr *Inst);
- void applyWaitcnt(const AMDGPU::Waitcnt &Wait);
+ void applyWaitcnt(const Waitcnt &Wait);
void applyWaitcnt(InstCounterType T, unsigned Count);
void updateByEvent(WaitEventType E, MachineInstr &MI);
@@ -866,13 +855,13 @@ class WaitcntBrackets {
};
void determineWaitForScore(InstCounterType T, unsigned Score,
- AMDGPU::Waitcnt &Wait) const;
+ Waitcnt &Wait) const;
static bool mergeScore(const MergeInfo &M, unsigned &Score,
unsigned OtherScore);
iterator_range<MCRegUnitIterator> regunits(MCPhysReg Reg) const {
- assert(Reg != AMDGPU::SCC && "Shouldn't be used on SCC");
+ assert(Reg != SCC && "Shouldn't be used on SCC");
if (!Context->TRI->isInAllocatableClass(Reg))
return {{}, {}};
const TargetRegisterClass *RC = Context->TRI->getPhysRegBaseClass(Reg);
@@ -901,7 +890,7 @@ class WaitcntBrackets {
void setRegScore(MCPhysReg Reg, InstCounterType T, unsigned Val) {
const SIRegisterInfo *TRI = Context->TRI;
- if (Reg == AMDGPU::SCC) {
+ if (Reg == SCC) {
SCCScore = Val;
} else if (TRI->isVectorRegister(*Context->MRI, Reg)) {
for (MCRegUnit RU : regunits(Reg))
@@ -1014,9 +1003,8 @@ bool WaitcntBrackets::hasPointSampleAccel(const MachineInstr &MI) const {
if (!Context->ST->hasPointSampleAccel() || !SIInstrInfo::isMIMG(MI))
return false;
- const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
- const AMDGPU::MIMGBaseOpcodeInfo *BaseInfo =
- AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
+ const MIMGInfo *Info = getMIMGInfo(MI.getOpcode());
+ const MIMGBaseOpcodeInfo *BaseInfo = getMIMGBaseOpcodeInfo(Info->BaseOpcode);
return BaseInfo->PointSampleAccel;
}
@@ -1057,20 +1045,18 @@ void WaitcntBrackets::updateByEvent(WaitEventType E, MachineInstr &Inst) {
if (TII->isDS(Inst) && Inst.mayLoadOrStore()) {
// All GDS operations must protect their address register (same as
// export.)
- if (const auto *AddrOp = TII->getNamedOperand(Inst, AMDGPU::OpName::addr))
+ if (const auto *AddrOp = TII->getNamedOperand(Inst, OpName::addr))
setScoreByOperand(*AddrOp, EXP_CNT, CurrScore);
if (Inst.mayStore()) {
- if (const auto *Data0 =
- TII->getNamedOperand(Inst, AMDGPU::OpName::data0))
+ if (const auto *Data0 = TII->getNamedOperand(Inst, OpName::data0))
setScoreByOperand(*Data0, EXP_CNT, CurrScore);
- if (const auto *Data1 =
- TII->getNamedOperand(Inst, AMDGPU::OpName::data1))
+ if (const auto *Data1 = TII->getNamedOperand(Inst, OpName::data1))
setScoreByOperand(*Data1, EXP_CNT, CurrScore);
} else if (SIInstrInfo::isAtomicRet(Inst) && !SIInstrInfo::isGWS(Inst) &&
- Inst.getOpcode() != AMDGPU::DS_APPEND &&
- Inst.getOpcode() != AMDGPU::DS_CONSUME &&
- Inst.getOpcode() != AMDGPU::DS_ORDERED_COUNT) {
+ Inst.getOpcode() != DS_APPEND &&
+ Inst.getOpcode() != DS_CONSUME &&
+ Inst.getOpcode() != DS_ORDERED_COUNT) {
for (const MachineOperand &Op : Inst.all_uses()) {
if (TRI->isVectorRegister(*MRI, Op.getReg()))
setScoreByOperand(Op, EXP_CNT, CurrScore);
@@ -1078,18 +1064,18 @@ void WaitcntBrackets::updateByEvent(WaitEventType E, MachineInstr &Inst) {
}
} else if (TII->isFLAT(Inst)) {
if (Inst.mayStore()) {
- setScoreByOperand(*TII->getNamedOperand(Inst, AMDGPU::OpName::data),
- EXP_CNT, CurrScore);
+ setScoreByOperand(*TII->getNamedOperand(Inst, OpName::data), EXP_CNT,
+ CurrScore);
} else if (SIInstrInfo::isAtomicRet(Inst)) {
- setScoreByOperand(*TII->getNamedOperand(Inst, AMDGPU::OpName::data),
- EXP_CNT, CurrScore);
+ setScoreByOperand(*TII->getNamedOperand(Inst, OpName::data), EXP_CNT,
+ CurrScore);
}
} else if (TII->isMIMG(Inst)) {
if (Inst.mayStore()) {
setScoreByOperand(Inst.getOperand(0), EXP_CNT, CurrScore);
} else if (SIInstrInfo::isAtomicRet(Inst)) {
- setScoreByOperand(*TII->getNamedOperand(Inst, AMDGPU::OpName::data),
- EXP_CNT, CurrScore);
+ setScoreByOperand(*TII->getNamedOperand(Inst, OpName::data), EXP_CNT,
+ CurrScore);
}
} else if (TII->isMTBUF(Inst)) {
if (Inst.mayStore())
@@ -1098,13 +1084,13 @@ void WaitcntBrackets::updateByEvent(WaitEventType E, MachineInstr &Inst) {
if (Inst.mayStore()) {
setScoreByOperand(Inst.getOperand(0), EXP_CNT, CurrScore);
} else if (SIInstrInfo::isAtomicRet(Inst)) {
- setScoreByOperand(*TII->getNamedOperand(Inst, AMDGPU::OpName::data),
- EXP_CNT, CurrScore);
+ setScoreByOperand(*TII->getNamedOperand(Inst, OpName::data), EXP_CNT,
+ CurrScore);
}
} else if (TII->isLDSDIR(Inst)) {
// LDSDIR instructions attach the score to the destination.
- setScoreByOperand(*TII->getNamedOperand(Inst, AMDGPU::OpName::vdst),
- EXP_CNT, CurrScore);
+ setScoreByOperand(*TII->getNamedOperand(Inst, OpName::vdst), EXP_CNT,
+ CurrScore);
} else {
if (TII->isEXP(Inst)) {
// For export the destination registers are really temps that
@@ -1221,7 +1207,7 @@ void WaitcntBrackets::updateByEvent(WaitEventType E, MachineInstr &Inst) {
}
if (SIInstrInfo::isSBarrierSCCWrite(Inst.getOpcode())) {
- setRegScore(AMDGPU::SCC, T, CurrScore);
+ setRegScore(SCC, T, CurrScore);
PendingSCCWrite = &Inst;
}
}
@@ -1331,8 +1317,8 @@ void WaitcntBrackets::print(raw_ostream &OS) const {
/// Simplify \p UpdateWait by removing waits that are redundant based on the
/// current WaitcntBrackets and any other waits specified in \p CheckWait.
-void WaitcntBrackets::simplifyWaitcnt(const AMDGPU::Waitcnt &CheckWait,
- AMDGPU::Waitcnt &UpdateWait) const {
+void WaitcntBrackets::simplifyWaitcnt(const Waitcnt &CheckWait,
+ Waitcnt &UpdateWait) const {
simplifyWaitcnt(LOAD_CNT, UpdateWait.LoadCnt);
simplifyWaitcnt(EXP_CNT, UpdateWait.ExpCnt);
simplifyWaitcnt(DS_CNT, UpdateWait.DsCnt);
@@ -1354,8 +1340,8 @@ void WaitcntBrackets::simplifyWaitcnt(InstCounterType T,
Count = ~0u;
}
-void WaitcntBrackets::simplifyXcnt(const AMDGPU::Waitcnt &CheckWait,
- AMDGPU::Waitcnt &UpdateWait) const {
+void WaitcntBrackets::simplifyXcnt(const Waitcnt &CheckWait,
+ Waitcnt &UpdateWait) const {
// Try to simplify xcnt further by checking for joint kmcnt and loadcnt
// optimizations. On entry to a block with multiple predescessors, there may
// be pending SMEM and VMEM events active at the same time.
@@ -1375,8 +1361,8 @@ void WaitcntBrackets::simplifyXcnt(const AMDGPU::Waitcnt &CheckWait,
simplifyWaitcnt(X_CNT, UpdateWait.XCnt);
}
-void WaitcntBrackets::simplifyVmVsrc(const AMDGPU::Waitcnt &CheckWait,
- AMDGPU::Waitcnt &UpdateWait) const {
+void WaitcntBrackets::simplifyVmVsrc(const Waitcnt &CheckWait,
+ Waitcnt &UpdateWait) const {
// Waiting for some counters implies waiting for VM_VSRC, since an
// instruction that decrements a counter on completion would have
// decremented VM_VSRC once its VGPR operands had been read.
@@ -1400,7 +1386,7 @@ void WaitcntBrackets::purgeEmptyTrackingData() {
void WaitcntBrackets::determineWaitForScore(InstCounterType T,
unsigned ScoreToWait,
- AMDGPU::Waitcnt &Wait) const {
+ Waitcnt &Wait) const {
const unsigned LB = getScoreLB(T);
const unsigned UB = getScoreUB(T);
@@ -1428,8 +1414,8 @@ void WaitcntBrackets::determineWaitForScore(InstCounterType T,
}
void WaitcntBrackets::determineWaitForPhysReg(InstCounterType T, MCPhysReg Reg,
- AMDGPU::Waitcnt &Wait) const {
- if (Reg == AMDGPU::SCC) {
+ Waitcnt &Wait) const {
+ if (Reg == SCC) {
determineWaitForScore(T, SCCScore, Wait);
} else {
bool IsVGPR = Context->TRI->isVectorRegister(*Context->MRI, Reg);
@@ -1441,7 +1427,7 @@ void WaitcntBrackets::determineWaitForPhysReg(InstCounterType T, MCPhysReg Reg,
}
void WaitcntBrackets::determineWaitForLDSDMA(InstCounterType T, VMEMID TID,
- AMDGPU::Waitcnt &Wait) const {
+ Waitcnt &Wait) const {
assert(TID >= LDSDMA_BEGIN && TID < LDSDMA_END);
determineWaitForScore(T, getVMemScore(TID, T), Wait);
}
@@ -1450,7 +1436,7 @@ void WaitcntBrackets::tryClearSCCWriteEvent(MachineInstr *Inst) {
// S_BARRIER_WAIT on the same barrier guarantees that the pending write to
// SCC has landed
if (PendingSCCWrite &&
- PendingSCCWrite->getOpcode() == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM &&
+ PendingSCCWrite->getOp...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/180663
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