[llvm] [LV] Add LoopVectorize/VPlan subdirectory for VPlan printing tests. (PR #180611)

via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 9 12:54:43 PST 2026 

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-transforms

Author: Florian Hahn (fhahn)

<details>
<summary>Changes</summary>

Add a new VPlan subdirectory as common place for tests checking VPlan printing. It contains a lit.local.cfg that only runs the tests when assertions are enabled.

This removes the need to add explicit REQUIRES: asserts to VPlan tests.

---
Full diff: https://github.com/llvm/llvm-project/pull/180611.diff


11 Files Affected:

- (renamed) llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-chains-vplan.ll (-1) 
- (renamed) llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll (-1) 
- (renamed) llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll (-2) 
- (added) llvm/test/Transforms/LoopVectorize/VPlan/lit.local.cfg (+4) 
- (renamed) llvm/test/Transforms/LoopVectorize/VPlan/phi-with-fastflags-vplan.ll (-1) 
- (renamed) llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll (-2) 
- (renamed) llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-before-execute.ll (-2) 
- (renamed) llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-metadata.ll (-1) 
- (renamed) llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll (-2) 
- (renamed) llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll (-1) 
- (renamed) llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll (-1) 


``````````diff
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll b/llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-chains-vplan.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-chains-vplan.ll
index 9ab2557387877..8d5caf250f3df 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-chains-vplan.ll
@@ -1,5 +1,4 @@
 ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
 
 ; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -debug-only=loop-vectorize -disable-output -S %s 2>&1 | FileCheck %s
 
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
index 6992a441f9444..075faa6a0056f 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
@@ -1,5 +1,4 @@
 ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
 ; RUN: opt < %s -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -force-widen-divrem-via-safe-divisor=0 -disable-output -debug-only=loop-vectorize 2>&1 | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll b/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
index 82470d3db0a2f..33294730933e7 100644
--- a/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
@@ -1,5 +1,3 @@
-; REQUIRES: asserts
-
 ; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -debug -disable-output %s 2>&1 | FileCheck --check-prefix=DBG %s
 ; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S %s | FileCheck %s
 
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/lit.local.cfg b/llvm/test/Transforms/LoopVectorize/VPlan/lit.local.cfg
new file mode 100644
index 0000000000000..9861880d9b5bb
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/lit.local.cfg
@@ -0,0 +1,4 @@
+config.suffixes = [".ll"]
+
+if not 'asserts' in config.available_features:
+    config.unsupported = True
diff --git a/llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll b/llvm/test/Transforms/LoopVectorize/VPlan/phi-with-fastflags-vplan.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/phi-with-fastflags-vplan.ll
index e451f94715610..f685bf806929c 100644
--- a/llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/phi-with-fastflags-vplan.ll
@@ -1,5 +1,4 @@
 ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
 ; RUN: opt -p loop-vectorize -force-vector-width=4 -debug-only=loop-vectorize -disable-output -S %s 2>&1 | FileCheck %s
 
 define void @f(ptr noalias %p, i1 %c) {
diff --git a/llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll b/llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
index be23acd443229..bee97a6955b3a 100644
--- a/llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
@@ -1,8 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
 ; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S -debug %s 2>&1 | FileCheck %s
 
-; REQUIRES: asserts
-
 declare void @init(ptr)
 
 define i64 @multi_exiting_to_different_exits_live_in_exit_values() {
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-before-execute.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-before-execute.ll
index 9ef3fd48efcd5..cb6937dc3e1ae 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-before-execute.ll
@@ -2,8 +2,6 @@
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
-; REQUIRES: asserts
-
 ; Check if the vector loop condition can be simplified to true for a given
 ; VF/IC combination.
 define void @test_tc_less_than_16(ptr %A, i64 %N) {
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-metadata.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-metadata.ll
index 027bfe859c828..990238b0b1c26 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-metadata.ll
@@ -1,5 +1,4 @@
 ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
 
 ; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s
 
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll
index 10c265519952b..481232386bb5c 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll
@@ -1,5 +1,3 @@
-; REQUIRES: asserts
-
 ; RUN: opt -passes=loop-vectorize -pass-remarks=loop-vectorize -enable-vplan-native-path -debug -disable-output %s 2>&1 | FileCheck %s
 
 @arr2 = external global [8 x i64], align 16
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
index b282a9079c996..0b002ed796374 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
@@ -1,5 +1,4 @@
 ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
 
 ; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -disable-output %s 2>&1 | FileCheck %s
 
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
similarity index 99%
rename from llvm/test/Transforms/LoopVectorize/vplan-printing.ll
rename to llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
index 1d5d71b0a64c0..f592c3f8e422d 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
@@ -1,5 +1,4 @@
 ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; REQUIRES: asserts
 
 ; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -enable-interleaved-mem-accesses=true -enable-masked-interleaved-mem-accesses -force-widen-divrem-via-safe-divisor=0 -disable-output %s 2>&1 | FileCheck --strict-whitespace %s
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/180611

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