[llvm] [AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (PR #175257)

[Petar Avramovic via llvm-commits]

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@@ -764,16 +760,26 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Uni(S64, {{Sgpr64}, {Sgpr64, Imm}})
       .Div(S64, {{Vgpr64}, {Vgpr64, Imm}});
 
-  // Atomic read-modify-write operations: result and value are always VGPR,
-  // pointer varies by address space.
   addRulesForGOpcs({G_ATOMICRMW_ADD, G_ATOMICRMW_SUB, G_ATOMICRMW_XCHG,
                     G_ATOMICRMW_AND, G_ATOMICRMW_OR, G_ATOMICRMW_XOR})
-      .Any({{S32, P0}, {{Vgpr32}, {VgprP0, Vgpr32}}})
-      .Any({{S64, P0}, {{Vgpr64}, {VgprP0, Vgpr64}}})
-      .Any({{S32, P1}, {{Vgpr32}, {VgprP1, Vgpr32}}})
-      .Any({{S64, P1}, {{Vgpr64}, {VgprP1, Vgpr64}}})
-      .Any({{S32, P3}, {{Vgpr32}, {VgprP3, Vgpr32}}})
-      .Any({{S64, P3}, {{Vgpr64}, {VgprP3, Vgpr64}}});
+      .Any({{DivS32, Ptr32, S32}, {{Vgpr32}, {VgprPtr32, Vgpr32}}})
+      .Any({{DivS32, Ptr64, S32}, {{Vgpr32}, {VgprPtr64, Vgpr32}}})
+      .Any({{DivS64, Ptr32, S64}, {{Vgpr64}, {VgprPtr32, Vgpr64}}})
+      .Any({{DivS64, Ptr64, S64}, {{Vgpr64}, {VgprPtr64, Vgpr64}}});
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petar-avramovic wrote:

remove from this patch?

https://github.com/llvm/llvm-project/pull/175257