[llvm] [CodeGen][AMDGPU] TwoAddress: Only skip undef COPY at REG_SEQUENCE lowering when there is Live info or no uses for subreg (PR #175598)
Felipe Quezada via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 9 05:50:08 PST 2026
https://github.com/kezada94 updated https://github.com/llvm/llvm-project/pull/175598
>From c16d786ffce537a8af7ab6cb5165bd1e3912c574 Mon Sep 17 00:00:00 2001
From: Felipe Quezada <felipe.quezada01 at outlook.com>
Date: Mon, 12 Jan 2026 15:04:51 -0300
Subject: [PATCH 1/6] [CodeGen][AMDGPU] TwoAddress: Propagate undef flag when
skipping COPY at REG_SEQUENCE lowering (#1)
* Lowering REG_SEQUENCE now propagates undef flag for skipped COPY's
* Fixed formatting
---
.../lib/CodeGen/TwoAddressInstructionPass.cpp | 8 +++++++
...ddr-regsequence-propagate-undef-on-use.mir | 22 +++++++++++++++++++
2 files changed, 30 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-propagate-undef-on-use.mir
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 5d919b5a8000c..fbb68c1670d62 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -2014,6 +2014,14 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
unsigned SubIdx = MI.getOperand(i+1).getImm();
// Nothing needs to be inserted for undef operands.
if (UseMO.isUndef()) {
+ // Propagate the undef flag to the next use (if any)
+ for (MachineOperand &Use : MRI->use_operands(DstReg)) {
+ if (Use.getSubReg() == SubIdx) {
+ Use.setIsUndef(true);
+ break;
+ }
+ }
+
UndefLanes |= TRI->getSubRegIndexLaneMask(SubIdx);
continue;
}
diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-propagate-undef-on-use.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-propagate-undef-on-use.mir
new file mode 100644
index 0000000000000..98f3731ee27f0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-propagate-undef-on-use.mir
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=twoaddressinstruction -o - %s | FileCheck %s
+
+# Checks that the undef flag of a src operand is correclty propagated when skipping COPY when
+# lowering REG_SEQUENCE
+
+---
+name: regsequence-propagate-undef-on-use
+noPhis: true
+body: |
+ bb.0:
+
+ ; CHECK-LABEL: name: regsequence-propagate-undef-on-use
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
+ ; CHECK-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[DEF]].sub1
+
+ %0:sgpr_32 = S_MOV_B32 0, implicit $exec
+
+ %3:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, undef %2:sgpr_32, %subreg.sub1
+ %12:vgpr_32 = V_MOV_B32_e32 %3.sub1, implicit $exec
+...
>From fa8c911e90146c2237521fce54dd60a6ec56af20 Mon Sep 17 00:00:00 2001
From: "Quezada Sanchez, Felipe" <felipe.quezada.sanchez at intel.com>
Date: Thu, 22 Jan 2026 09:38:08 -0800
Subject: [PATCH 2/6] New approach: only skip COPY when its safe to do so
---
.../lib/CodeGen/TwoAddressInstructionPass.cpp | 27 ++++++++++++-------
... twoaddr-regsequence-keep-copy-on-use.mir} | 3 ++-
2 files changed, 20 insertions(+), 10 deletions(-)
rename llvm/test/CodeGen/AMDGPU/{twoaddr-regsequence-propagate-undef-on-use.mir => twoaddr-regsequence-keep-copy-on-use.mir} (84%)
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index fbb68c1670d62..256af30ca8217 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -2006,6 +2006,18 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
}
}
+ // If there are no live intervals information, we scan the use list once
+ // in order to find which subregisters are used.
+ LaneBitmask UsedLanes = LaneBitmask::getNone();
+ if (!LIS) {
+ for (MachineOperand &Use : MRI->use_nodbg_operands(DstReg)) {
+ auto SubReg = Use.getSubReg();
+ if (SubReg) {
+ UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
+ }
+ }
+ }
+
LaneBitmask UndefLanes = LaneBitmask::getNone();
bool DefEmitted = false;
for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
@@ -2013,17 +2025,14 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
Register SrcReg = UseMO.getReg();
unsigned SubIdx = MI.getOperand(i+1).getImm();
// Nothing needs to be inserted for undef operands.
+ // Unless there's no live intervals, and they are used at a later
+ // instruction as operand.
if (UseMO.isUndef()) {
- // Propagate the undef flag to the next use (if any)
- for (MachineOperand &Use : MRI->use_operands(DstReg)) {
- if (Use.getSubReg() == SubIdx) {
- Use.setIsUndef(true);
- break;
- }
+ LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubIdx);
+ if (LIS || (UsedLanes & LaneMask).none()) {
+ UndefLanes |= LaneMask;
+ continue;
}
-
- UndefLanes |= TRI->getSubRegIndexLaneMask(SubIdx);
- continue;
}
// Defer any kill flag to the last operand using SrcReg. Otherwise, we
diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-propagate-undef-on-use.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
similarity index 84%
rename from llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-propagate-undef-on-use.mir
rename to llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
index 98f3731ee27f0..d0f7a460a247d 100644
--- a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-propagate-undef-on-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
@@ -13,7 +13,8 @@ body: |
; CHECK-LABEL: name: regsequence-propagate-undef-on-use
; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
- ; CHECK-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[DEF]].sub1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]].sub1:sreg_64 = COPY undef [[UND:%[0-9]+]]:sgpr_32
+ ; CHECK-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 [[DEF]].sub1
%0:sgpr_32 = S_MOV_B32 0, implicit $exec
>From 309e924e176b12ea336174a4e3cf08d7a2be1a76 Mon Sep 17 00:00:00 2001
From: "Quezada Sanchez, Felipe" <felipe.quezada.sanchez at intel.com>
Date: Thu, 22 Jan 2026 10:03:26 -0800
Subject: [PATCH 3/6] Updated LIT test comments
---
.../AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
index d0f7a460a247d..bb9085838c2f3 100644
--- a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
@@ -1,16 +1,16 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=twoaddressinstruction -o - %s | FileCheck %s
-# Checks that the undef flag of a src operand is correclty propagated when skipping COPY when
-# lowering REG_SEQUENCE
+# Checks that while lowering REG_SEQUENCE, undef COPY are not skipped if there is no LIS
+# information
---
-name: regsequence-propagate-undef-on-use
+name: regsequence-keep-copy-on-use
noPhis: true
body: |
bb.0:
- ; CHECK-LABEL: name: regsequence-propagate-undef-on-use
+ ; CHECK-LABEL: name: regsequence-keep-copy-on-use
; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
; CHECK-NEXT: [[DEF:%[0-9]+]].sub1:sreg_64 = COPY undef [[UND:%[0-9]+]]:sgpr_32
>From 2b6a55802dae45bd7414d94ff763be7e5f68036d Mon Sep 17 00:00:00 2001
From: "Quezada Sanchez, Felipe" <felipe.quezada.sanchez at intel.com>
Date: Fri, 23 Jan 2026 09:51:32 -0800
Subject: [PATCH 4/6] Added more tests with and without LIS info, also updated
comments
---
.../lib/CodeGen/TwoAddressInstructionPass.cpp | 4 +-
.../twoaddr-regsequence-keep-copy-on-use.mir | 58 +++++++++++++++++--
2 files changed, 54 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 256af30ca8217..1d09de1774989 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -2011,7 +2011,7 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
LaneBitmask UsedLanes = LaneBitmask::getNone();
if (!LIS) {
for (MachineOperand &Use : MRI->use_nodbg_operands(DstReg)) {
- auto SubReg = Use.getSubReg();
+ unsigned SubReg = Use.getSubReg();
if (SubReg) {
UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
}
@@ -2025,7 +2025,7 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
Register SrcReg = UseMO.getReg();
unsigned SubIdx = MI.getOperand(i+1).getImm();
// Nothing needs to be inserted for undef operands.
- // Unless there's no live intervals, and they are used at a later
+ // Unless there are no live intervals, and they are used at a later
// instruction as operand.
if (UseMO.isUndef()) {
LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubIdx);
diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
index bb9085838c2f3..c1611f56995de 100644
--- a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
@@ -1,23 +1,69 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=twoaddressinstruction -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=twoaddressinstruction -o - %s | FileCheck -check-prefix=CHECK %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=liveintervals,twoaddressinstruction -o - %s | FileCheck -check-prefix=LIS %s
# Checks that while lowering REG_SEQUENCE, undef COPY are not skipped if there is no LIS
# information
---
-name: regsequence-keep-copy-on-use
+name: regsequence-undef-subreg-use
noPhis: true
body: |
bb.0:
- ; CHECK-LABEL: name: regsequence-keep-copy-on-use
+ ; CHECK-LABEL: name: regsequence-undef-subreg-use
; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
; CHECK-NEXT: [[DEF:%[0-9]+]].sub1:sreg_64 = COPY undef [[UND:%[0-9]+]]:sgpr_32
; CHECK-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 [[DEF]].sub1
+ ; LIS-LABEL: name: regsequence-undef-subreg-use
+ ; LIS: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; LIS-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
+ ; LIS-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[DEF]].sub1
+
+ %0:sgpr_32 = S_MOV_B32 0, implicit $exec
+
+ %1:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, undef %2:sgpr_32, %subreg.sub1
+ %3:vgpr_32 = V_MOV_B32_e32 %1.sub1, implicit $exec
+...
+
+---
+name: regsequence-undef-subreg-without-use
+noPhis: true
+body: |
+ bb.0:
+
+ ; CHECK-LABEL: name: regsequence-undef-subreg-without-use
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
+
+ ; LIS-LABEL: name: regsequence-undef-subreg-without-use
+ ; LIS: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; LIS-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
+
+ %0:sgpr_32 = S_MOV_B32 0, implicit $exec
+
+ %1:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, undef %2:sgpr_32, %subreg.sub1
+...
+
+---
+name: regsequence-undef-subreg-full-reg-use
+noPhis: true
+body: |
+ bb.0:
+
+ ; CHECK-LABEL: name: regsequence-undef-subreg-full-reg-use
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
+ ; CHECK-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = COPY [[DEF]], implicit $exec
+
+ ; LIS-LABEL: name: regsequence-undef-subreg-full-reg-use
+ ; LIS: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; LIS-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
+ ; LIS-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = COPY [[DEF]], implicit $exec
+
%0:sgpr_32 = S_MOV_B32 0, implicit $exec
- %3:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, undef %2:sgpr_32, %subreg.sub1
- %12:vgpr_32 = V_MOV_B32_e32 %3.sub1, implicit $exec
+ %1:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, undef %2:sgpr_32, %subreg.sub1
+ %3:vgpr_32 = COPY %1, implicit $exec
...
>From 497ccce6b5cd784d9753d741a6ed303df6d81926 Mon Sep 17 00:00:00 2001
From: Felipe Quezada <felipe.quezada01 at outlook.com>
Date: Mon, 26 Jan 2026 10:48:30 -0300
Subject: [PATCH 5/6] Update
llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
Fixed lit test COPY dst
Co-authored-by: Carl Ritson <critson at perlfu.co.uk>
---
.../CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
index c1611f56995de..ec82c7dc50736 100644
--- a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
@@ -65,5 +65,5 @@ body: |
%0:sgpr_32 = S_MOV_B32 0, implicit $exec
%1:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, undef %2:sgpr_32, %subreg.sub1
- %3:vgpr_32 = COPY %1, implicit $exec
+ %3:vreg_64 = COPY %1, implicit $exec
...
>From 8e05deea3c4366ad0ee828191792c1ca37d6f03e Mon Sep 17 00:00:00 2001
From: "Quezada Sanchez, Felipe" <felipe.quezada.sanchez at intel.com>
Date: Mon, 9 Feb 2026 05:49:50 -0800
Subject: [PATCH 6/6] Fixed test checks dst register and updated code
---
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 4 +---
.../CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir | 4 ++--
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 1d09de1774989..177c2d07c0537 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -2011,10 +2011,8 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
LaneBitmask UsedLanes = LaneBitmask::getNone();
if (!LIS) {
for (MachineOperand &Use : MRI->use_nodbg_operands(DstReg)) {
- unsigned SubReg = Use.getSubReg();
- if (SubReg) {
+ if (unsigned SubReg = Use.getSubReg())
UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
- }
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
index ec82c7dc50736..f28310536bd49 100644
--- a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
@@ -55,12 +55,12 @@ body: |
; CHECK-LABEL: name: regsequence-undef-subreg-full-reg-use
; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
- ; CHECK-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = COPY [[DEF]], implicit $exec
+ ; CHECK-NEXT: [[OTH:%[0-9]+]]:vreg_64 = COPY [[DEF]], implicit $exec
; LIS-LABEL: name: regsequence-undef-subreg-full-reg-use
; LIS: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
; LIS-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
- ; LIS-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = COPY [[DEF]], implicit $exec
+ ; LIS-NEXT: [[OTH:%[0-9]+]]:vreg_64 = COPY [[DEF]], implicit $exec
%0:sgpr_32 = S_MOV_B32 0, implicit $exec
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