[llvm] [RegisterCoalescer] The COPY with the implicit-def of super register is not coalescable. (PR #169997)

[via llvm-commits]

https://github.com/dianqk updated https://github.com/llvm/llvm-project/pull/169997

>From 7e0dccf4303c05d1158a5865c12f4a1387407f07 Mon Sep 17 00:00:00 2001
From: dianqk <dianqk at dianqk.net>
Date: Sat, 29 Nov 2025 21:14:49 +0800
Subject: [PATCH 1/2] Pre-commit test cases

---
 .../CodeGen/X86/coalesce-implicit-def.mir     | 20 +++++++++++++++++++
 llvm/test/CodeGen/X86/pr169996.ll             | 19 ++++++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/coalesce-implicit-def.mir
 create mode 100644 llvm/test/CodeGen/X86/pr169996.ll

diff --git a/llvm/test/CodeGen/X86/coalesce-implicit-def.mir b/llvm/test/CodeGen/X86/coalesce-implicit-def.mir
new file mode 100644
index 0000000000000..952af13a680d0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/coalesce-implicit-def.mir
@@ -0,0 +1,20 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -run-pass register-coalescer -mtriple x86_64-unknown-linux-gnu -o - %s | FileCheck %s
+
+---
+name:            fn1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: fn1
+    ; CHECK: liveins: $rdi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
+    ; CHECK-NEXT: $rax = COPY [[COPY]]
+    %0:gr64_with_sub_8bit = COPY $rdi
+    undef %1.sub_32bit:gr64_with_sub_8bit = COPY %0.sub_32bit, implicit-def %1
+    $rax = COPY %1
+...
+
diff --git a/llvm/test/CodeGen/X86/pr169996.ll b/llvm/test/CodeGen/X86/pr169996.ll
new file mode 100644
index 0000000000000..71e50489afd4d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr169996.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+; FIXME: The first instruction should be `movl %edi, %eax`.
+
+define i64 @fn1(i64 %arg, ptr %arg1) {
+; CHECK-LABEL: fn1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    movb (%rsi), %al
+; CHECK-NEXT:    retq
+  %i = trunc i64 %arg to i32
+  %i4 = load i8, ptr %arg1
+  %i5 = zext i8 %i4 to i32
+  %i6 = and i32 %i, -256
+  %i7 = or i32 %i6, %i5
+  %i12 = zext i32 %i7 to i64
+  ret i64 %i12
+}

>From 7b3d9f1f68f507ddbd1aaa85a15bd3273a5b8bd1 Mon Sep 17 00:00:00 2001
From: dianqk <dianqk at dianqk.net>
Date: Sat, 29 Nov 2025 21:34:09 +0800
Subject: [PATCH 2/2] [RegisterCoalescer] The COPY with the implicit-def of
 super register is not coalescable.

---
 llvm/lib/CodeGen/RegisterCoalescer.cpp          | 10 ++++++++++
 llvm/test/CodeGen/X86/coalesce-implicit-def.mir |  6 +++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 586c27b7e3baf..cd1099ab725c1 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -505,6 +505,16 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
       if (Src == Dst && SrcSub != DstSub)
         return false;
 
+      // A dependence involving an implicit-def on the high bits needs to be
+      // preserved.
+      for (unsigned I = MI->getDesc().getNumOperands(),
+                    E = MI->getNumOperands();
+           I != E; ++I) {
+        const MachineOperand &MO = MI->getOperand(I);
+        if (MO.isReg() && MO.isDef() && MO.getReg() == Dst)
+          return false;
+      }
+
       NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, SrcIdx,
                                          DstIdx);
       if (!NewRC)
diff --git a/llvm/test/CodeGen/X86/coalesce-implicit-def.mir b/llvm/test/CodeGen/X86/coalesce-implicit-def.mir
index 952af13a680d0..bd9de3b933394 100644
--- a/llvm/test/CodeGen/X86/coalesce-implicit-def.mir
+++ b/llvm/test/CodeGen/X86/coalesce-implicit-def.mir
@@ -1,6 +1,9 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
 # RUN: llc -run-pass register-coalescer -mtriple x86_64-unknown-linux-gnu -o - %s | FileCheck %s
 
+# Checks that we do not merge %1 into %0.
+# `undef %1.sub_32bit = COPY %0.sub_32bit, implicit-def %1` is zero extended.
+
 ---
 name:            fn1
 tracksRegLiveness: true
@@ -12,7 +15,8 @@ body:             |
     ; CHECK: liveins: $rdi
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
-    ; CHECK-NEXT: $rax = COPY [[COPY]]
+    ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = COPY [[COPY]].sub_32bit, implicit-def [[COPY1]]
+    ; CHECK-NEXT: $rax = COPY [[COPY1]]
     %0:gr64_with_sub_8bit = COPY $rdi
     undef %1.sub_32bit:gr64_with_sub_8bit = COPY %0.sub_32bit, implicit-def %1
     $rax = COPY %1