[llvm] [MachineScheduler] Add an option to split regions into chunks of a given maximum size (PR #180519)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Nathan Corbyn (cofibrant)

<details>
<summary>Changes</summary>

Adds an option to the machine scheduler (`-misched-max-region-instrs=N`) setting the maximum number of instructions in a scheduling region. In case `N == 0`, the option is ignored. If the number of instructions in a region would otherwise exceed `N`, the region is split into chunks of at most `N` instructions. As implemented, if the number of instructions is `K`, the first `K / N` chunks contain `N` instructions and the final chunk (if applicable) contains the remaining `K % N` instructions.

---
Full diff: https://github.com/llvm/llvm-project/pull/180519.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/MachineScheduler.cpp (+9-4) 
- (added) llvm/test/CodeGen/AArch64/misched-max-region-size.mir (+51) 


``````````diff
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 05df5ea59d7a3..3e26562778ed8 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -249,6 +249,11 @@ static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden,
 static cl::opt<unsigned> ReadyListLimit("misched-limit", cl::Hidden,
   cl::desc("Limit ready list to N instructions"), cl::init(256));
 
+static cl::opt<unsigned> MaxRegionInstrs(
+    "misched-max-region-instrs", cl::Hidden,
+    cl::desc("Split regions larger than N instructions. 0 disables."),
+    cl::init(0));
+
 static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
   cl::desc("Enable register pressure scheduling."), cl::init(true));
 
@@ -784,10 +789,9 @@ getSchedRegions(MachineBasicBlock *MBB,
       RegionEnd != MBB->begin(); RegionEnd = I) {
 
     // Avoid decrementing RegionEnd for blocks with no terminator.
-    if (RegionEnd != MBB->end() ||
-        isSchedBoundary(&*std::prev(RegionEnd), &*MBB, MF, TII)) {
+    if (RegionEnd != MBB->end() &&
+        isSchedBoundary(&*std::prev(RegionEnd), &*MBB, MF, TII))
       --RegionEnd;
-    }
 
     // The next region starts above the previous region. Look backward in the
     // instruction stream until we find the nearest boundary.
@@ -795,7 +799,8 @@ getSchedRegions(MachineBasicBlock *MBB,
     I = RegionEnd;
     for (;I != MBB->begin(); --I) {
       MachineInstr &MI = *std::prev(I);
-      if (isSchedBoundary(&MI, &*MBB, MF, TII))
+      if (isSchedBoundary(&MI, &*MBB, MF, TII) ||
+          (MaxRegionInstrs && NumRegionInstrs >= MaxRegionInstrs))
         break;
       if (!MI.isDebugOrPseudoInstr()) {
         // MBB::size() uses instr_iterator to count. Here we need a bundle to
diff --git a/llvm/test/CodeGen/AArch64/misched-max-region-size.mir b/llvm/test/CodeGen/AArch64/misched-max-region-size.mir
new file mode 100644
index 0000000000000..99c124bc5e445
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/misched-max-region-size.mir
@@ -0,0 +1,51 @@
+# RUN: llc -mtriple=arm64-apple-ios -run-pass=machine-scheduler -debug-only=machine-scheduler -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=CHECK-DEFAULT
+# RUN: llc -mtriple=arm64-apple-ios -run-pass=machine-scheduler -misched-max-region-instrs=3 -debug-only=machine-scheduler -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=CHECK-SPLIT
+
+# REQUIRES: asserts
+
+# Test that -misched-max-region-size splits large scheduling regions.
+
+# test_region_split_even
+# CHECK-DEFAULT: RegionInstrs: 6
+# CHECK-SPLIT: RegionInstrs: 3
+# CHECK-SPLIT: RegionInstrs: 3
+
+# test_region_split_uneven: 8 instructions, splits into 3+3+2
+# CHECK-DEFAULT: RegionInstrs: 8
+# CHECK-SPLIT: RegionInstrs: 3
+# CHECK-SPLIT: RegionInstrs: 3
+# CHECK-SPLIT: RegionInstrs: 2
+
+# CHECK-DEFAULT-NOT: RegionInstrs:
+# CHECK-SPLIT-NOT: RegionInstrs:
+
+---
+name: test_region_split_even
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0, $x1, $x2, $x3, $x4, $x5
+    $x10 = ADDXrr $x0, $x1
+    $x11 = ADDXrr $x2, $x3
+    $x12 = ADDXrr $x4, $x5
+    $x13 = SUBXrr $x0, $x1
+    $x14 = SUBXrr $x2, $x3
+    $x15 = SUBXrr $x4, $x5
+    RET_ReallyLR
+...
+---
+name: test_region_split_uneven
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
+    $x10 = ADDXrr $x0, $x1
+    $x11 = ADDXrr $x2, $x3
+    $x12 = ADDXrr $x4, $x5
+    $x13 = SUBXrr $x0, $x1
+    $x14 = SUBXrr $x2, $x3
+    $x15 = SUBXrr $x4, $x5
+    $x16 = ANDXrr $x0, $x6
+    $x17 = ORRXrr $x0, $x7
+    RET_ReallyLR
+...

``````````

</details>


https://github.com/llvm/llvm-project/pull/180519