[llvm] [RISCV] Enable select optimization by default (PR #178394)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 9 02:13:37 PST 2026
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/178394
>From b498c9c5783096148de50d91f152d25b2ce44bd3 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Tue, 27 Jan 2026 15:12:58 +0800
Subject: [PATCH 1/4] [RISCV] Enable select optimization by default
And we adds `FeatureEnableSelectOptimize` to `generic-ooo`.
---
llvm/lib/Target/RISCV/RISCVProcessors.td | 3 ++-
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +-
llvm/test/CodeGen/RISCV/O3-pipeline.ll | 9 +++++++++
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index fba8f79a19fbe..39f18266bd78f 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -103,7 +103,8 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
// Support generic for compatibility with other targets. The triple will be used
// to change to the appropriate rv32/rv64 version.
def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo;
-def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel>,
+def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel,
+ [FeatureEnableSelectOptimize]>,
GenericTuneInfo;
// clang-format off
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 7eb56f52c2e66..7b13c0331f730 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -112,7 +112,7 @@ static cl::opt<bool> EnableCFIInstrInserter(
static cl::opt<bool>
EnableSelectOpt("riscv-select-opt", cl::Hidden,
cl::desc("Enable select to branch optimizations"),
- cl::init(false));
+ cl::init(true));
extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 3b63c1d86d3b1..c2264862c89a9 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -72,6 +72,15 @@
; CHECK-NEXT: Scalarize Masked Memory Intrinsics
; CHECK-NEXT: Expand reduction intrinsics
; CHECK-NEXT: Natural Loop Information
+; CHECK-NEXT: Post-Dominator Tree Construction
+; CHECK-NEXT: Branch Probability Analysis
+; CHECK-NEXT: Block Frequency Analysis
+; CHECK-NEXT: Lazy Branch Probability Analysis
+; CHECK-NEXT: Lazy Block Frequency Analysis
+; CHECK-NEXT: Optimization Remark Emitter
+; CHECK-NEXT: Optimize selects
+; CHECK-NEXT: Dominator Tree Construction
+; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Type Promotion
; CHECK-NEXT: CodeGen Prepare
; CHECK-NEXT: Dominator Tree Construction
>From 2c34ebaf6227d00211c688304e9a6b4fdec49080 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Wed, 28 Jan 2026 17:56:49 +0800
Subject: [PATCH 2/4] [RISCV] Enable FeatureEnableSelectOptimize for
sifive-p550 and spacemit-x60
---
llvm/lib/Target/RISCV/RISCVProcessors.td | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 39f18266bd78f..bdbddf23baa11 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -434,7 +434,8 @@ def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", SiFiveP500Model,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtZba,
- FeatureStdExtZbb],
+ FeatureStdExtZbb,
+ FeatureEnableSelectOptimize],
SiFiveP500TuneFeatures> {
let MVendorID = 0x489;
let MArchID = 0x8000000000000008;
@@ -757,7 +758,8 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
FeatureStdExtZvkt,
FeatureStdExtZvl256b,
FeatureVendorXSMTVDot,
- FeatureUnalignedScalarMem]),
+ FeatureUnalignedScalarMem,
+ FeatureEnableSelectOptimize]),
[TuneDLenFactor2,
TuneOptimizedNF2SegmentLoadStore,
TuneOptimizedNF3SegmentLoadStore,
>From 9a049e45c0585ef2a13c8dccec046f4b0f9519ae Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Wed, 4 Feb 2026 17:35:33 +0800
Subject: [PATCH 3/4] Add RUN lines with -mcpu
---
llvm/test/CodeGen/RISCV/selectopt.ll | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/selectopt.ll b/llvm/test/CodeGen/RISCV/selectopt.ll
index e82037bb59e20..dba171e4bf8f8 100644
--- a/llvm/test/CodeGen/RISCV/selectopt.ll
+++ b/llvm/test/CodeGen/RISCV/selectopt.ll
@@ -8,6 +8,12 @@
; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \
; RUN: -mtriple=riscv64 -mattr=+enable-select-opt,+predictable-select-expensive -S < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,SELECT-OPT,SELECT-OPT-EXPENSIVE
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \
+; RUN: -mtriple=riscv64 -mcpu=spacemit-x60 -S < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,SELECT-OPT,SELECT-OPT-NOT-EXPENSIVE,SPACEMIT-X60
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \
+; RUN: -mtriple=riscv64 -mcpu=sifive-p550 -S < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,SELECT-OPT,SELECT-OPT-NOT-EXPENSIVE,SIFIVE-P550
%struct.st = type { i32, i64, ptr, ptr, i16, ptr, ptr, i64, i64 }
@@ -956,3 +962,5 @@ exit:
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; SELECT-OPT-EXPENSIVE: {{.*}}
; SELECT-OPT-NOT-EXPENSIVE: {{.*}}
+; SIFIVE-P550: {{.*}}
+; SPACEMIT-X60: {{.*}}
>From 2e1709c8de98b08aac53f438c583ec984652cb4b Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Mon, 9 Feb 2026 18:13:21 +0800
Subject: [PATCH 4/4] Add FeatureEnableSelectOptimize to GenericTuneFeatures
---
llvm/lib/Target/RISCV/RISCVProcessors.td | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index bdbddf23baa11..ae95a82bbe153 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -86,7 +86,8 @@ class RISCVTuneProcessorModel<string n,
list<SubtargetFeature> f = []>
: ProcessorModel<n, m, f,tunef>;
-defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
+defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore,
+ FeatureEnableSelectOptimize];
def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
NoSchedModel,
@@ -103,8 +104,7 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
// Support generic for compatibility with other targets. The triple will be used
// to change to the appropriate rv32/rv64 version.
def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo;
-def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel,
- [FeatureEnableSelectOptimize]>,
+def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel>,
GenericTuneInfo;
// clang-format off
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