[llvm] [X86] Fix lower1BitShuffle blend-with-zero shuffles to AND mask (PR #180472)

[Simon Pilgrim via llvm-commits]

RKSimon wrote:

@woruyu BUILD_VECTOR, INSERT_VECTOR_ELT and EXTRACT_VECTOR_ELT permit INTEGER scalar types to be wider than the vector element type to allow for legality - you'll find references to implicit truncation in DAG code that refers to this.

https://github.com/llvm/llvm-project/pull/180472