[llvm] [RISCV] Update Andes45 vector fixed-point arithmetic scheduling info (PR #180451)
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Sun Feb 8 17:55:32 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Jim Lin (tclin914)
<details>
<summary>Changes</summary>
This PR adds latency/throughput for all RVV fixed-point arithmetic to the andes45 series scheduling model.
---
Patch is 566.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/180451.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVSchedAndes45.td (+23-13)
- (modified) llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s (+613-613)
- (modified) llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s (+349-349)
- (modified) llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s (+69-69)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index e183ad947a0a1..bb127509e2a29 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -761,27 +761,37 @@ foreach mx = SchedMxListW in {
// 12. Vector Fixed-Point Arithmetic Instructions
foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
- defm "" : LMULWriteResMX<"WriteVSALUV", [Andes45VALU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSALUX", [Andes45VALU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSALUI", [Andes45VALU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVAALUV", [Andes45VALU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVAALUX", [Andes45VALU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSMulV", [Andes45VMAC], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSMulX", [Andes45VMAC], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSShiftV", [Andes45VALU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSShiftX", [Andes45VALU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSShiftI", [Andes45VALU], mx, IsWorstCase>;
+ let Latency = 2, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVSALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftI", [Andes45VALU], mx, IsWorstCase>;
+ }
+
+ let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVSMulV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulX", [Andes45VMAC], mx, IsWorstCase>;
+ }
}
// Narrowing
foreach mx = SchedMxListW in {
+ defvar Latency = Andes45GetLatencyNarrowing<mx>.c;
+ defvar Cycles = Andes45GetCyclesNarrowing<mx>.c;
defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListW>.c;
- defm "" : LMULWriteResMX<"WriteVNClipV", [Andes45VALU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVNClipX", [Andes45VALU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVNClipI", [Andes45VALU], mx, IsWorstCase>;
+ let Latency = Latency, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVNClipV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipI", [Andes45VALU], mx, IsWorstCase>;
+ }
}
// 13. Vector Floating-Point Instructions
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s
index e7d76cf49e06d..c8337e0c9bc61 100644
--- a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s
@@ -3010,357 +3010,357 @@ vwsub.wx v8, v16, x30
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_VX vwsub.vx v8, v16, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAADDU_VV vaaddu.vv v8, v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAADDU_VX vaaddu.vx v8, v8, t5
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/180451
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