[llvm] [Mips] Custom lowering of SET_ROUNDING, GET_ROUNDING (PR #170047)

[Matt Arsenault via llvm-commits]

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@@ -62,6 +65,10 @@ def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
 
 // Node used to generate an MTC1 i32 to f64 instruction
 def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>;
+def MipsReadFCSR : SDNode<"MipsISD::ReadFCSR", SDT_MipsReadFCSR,
+                             [SDNPHasChain]>;
+def MipsWriteFCSR : SDNode<"MipsISD::WriteFCSR", SDT_MipsWriteFCSR,
+                              [SDNPHasChain, SDNPSideEffect]>;
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arsenm wrote:

> Current implementation uses pseudos to address this issue by assigning Uses/Defs of FCR31 to the pseudos, without modifying the existing instructions. Perhaps I misunderstood your comment on pseudos, in which case please let me know.

This implementation is directly expanding the pseudos after instruction selection to CFC1/ CTC1/CFC1_MM/CTC1_MM. If you can do that, you can equivalently directly use those with getMachineNode in the custom lowering . The output of the pseudo expansion needs to have the correct register dependency, the DAG temporary node is an unnecessary level of indirection. If the register dependencies are missing from those final instructions, this is broken anyway 

https://github.com/llvm/llvm-project/pull/170047