[llvm] [AMDGPU] Insert readfirstlane for uniform VGPR arguments (PR #178198)

[Shilei Tian via llvm-commits]

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@@ -3627,6 +3627,14 @@ SDValue SITargetLowering::LowerFormalArguments(
 
     Reg = MF.addLiveIn(Reg, RC);
     SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
+    if (Arg.Flags.isInReg() && RC == &AMDGPU::VGPR_32RegClass) {
+      // FIXME: Need to forward the chains created by `CopyFromReg`s, make sure
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shiltian wrote:

Is this FIXME still relavant?

https://github.com/llvm/llvm-project/pull/178198