[llvm] [AArch64][ISel] Lower fixed-width i64 vector CLMUL intrinsics (PR #178876)

[Matthew Devereau via llvm-commits]

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@@ -11795,6 +11795,19 @@ let Predicates = [HasTEV] in {
   defm TEXIT : TEXIT<"texit">;
 }
 
+// Patterns for v2i64/v1i64 clmul->pmull
+def : Pat<(clmul v1i64:$Rn, v1i64:$Rd),
+          (v1i64 (EXTRACT_SUBREG (v16i8 (PMULLv1i64 $Rn, $Rd)),
+                                        (i32 3)))>;
+
+def : Pat<(clmul v2i64:$Rn, v2i64:$Rd),
+          (v2i64 (INSvi64lane (v16i8 (PMULLv1i64 (v1i64 (EXTRACT_SUBREG $Rn, (i32 3))),
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MDevereau wrote:

I've done the dsub change but left the overall pattern structure. I wasn't sure if you want me to try and remove the insert still, or just leave it as is.

https://github.com/llvm/llvm-project/pull/178876