[llvm] [AMDGPU] Add DPP16 Row Share optimization for llvm.amdgcn.wave.shuffle (PR #177470)

[Jay Foad via llvm-commits]

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@@ -1759,6 +1842,12 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
     NewII->copyMetadata(II);
     return IC.eraseInstFromFunction(II);
   }
+  case Intrinsic::amdgcn_wave_shuffle: {
+    if (!ST->hasDPP())
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jayfoad wrote:

Nit: isn't this redundant since you also check it inside tryWaveShuffleDPP?

https://github.com/llvm/llvm-project/pull/177470