[llvm] [ARM] Use REG_SEQUENCE instead of SUBREG_TO_REG for crypto patterns. NFCI. (PR #179910)

[Jay Foad via llvm-commits]

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@@ -7403,26 +7403,34 @@ def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
 let Predicates = [HasNEON] in {
 def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)),
           (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
-              (SHA1H (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
-                                    ssub_0)),
+              (SHA1H (REG_SEQUENCE QPR, (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)), ssub_0,
+                                        (i32 (IMPLICIT_DEF)), ssub_1,
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jayfoad wrote:

I note that the DAG selection pattern for this instruction is `(set QPR:$Vd, (v4i32 (null_frag (v4i32 QPR:$Vm))))` so it seems to be based on v4i32 not v4f32. So I'm really not sure where this `f32` usage comes from in the first place.

https://github.com/llvm/llvm-project/pull/179910