[llvm] [ARM] Use REG_SEQUENCE instead of SUBREG_TO_REG for crypto patterns. NFCI. (PR #179910)

[Eli Friedman via llvm-commits]

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@@ -7403,26 +7403,34 @@ def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
 let Predicates = [HasNEON] in {
 def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)),
           (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
-              (SHA1H (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
-                                    ssub_0)),
+              (SHA1H (REG_SEQUENCE QPR, (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)), ssub_0,
+                                        (i32 (IMPLICIT_DEF)), ssub_1,
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efriedma-quic wrote:

I'm a bit surprised `i32 (IMPLICIT_DEF)` actually works, since that would normally end up in an integer register.

Please fix the testing so it shows we don't generate any unexpected instructions.  The only test we currently have is llvm/test/CodeGen/ARM/intrinsics-crypto.ll, which is extremely barebones.

https://github.com/llvm/llvm-project/pull/179910