[llvm] 744827e - [X86] Fixed truncated masked stores (#179853)

[via llvm-commits]

Author: Phoebe Wang
Date: 2026-02-05T21:06:17+08:00
New Revision: 744827e22f1bfdd092d336cbcc34d65ad9abad51

URL: https://github.com/llvm/llvm-project/commit/744827e22f1bfdd092d336cbcc34d65ad9abad51
DIFF: https://github.com/llvm/llvm-project/commit/744827e22f1bfdd092d336cbcc34d65ad9abad51.diff

LOG: [X86] Fixed truncated masked stores (#179853)

Fixes: #179489

Added: 
    llvm/test/CodeGen/X86/pr179489.ll

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index aa04250eec92c..53d1427d516c9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -54167,8 +54167,8 @@ static SDValue combineMaskedLoad(SDNode *N, SelectionDAG &DAG,
   return SDValue();
 }
 
-/// If exactly one element of the mask is set for a non-truncating masked store,
-/// it is a vector extract and scalar store.
+/// If exactly one element of the mask is set for a masked store, it is a vector
+/// extract, truncate (iff truncating store) and scalar store.
 /// Note: It is expected that the degenerate cases of an all-zeros or all-ones
 /// mask have already been optimized in IR, so we don't bother with those here.
 static SDValue reduceMaskedStoreToScalarStore(MaskedStoreSDNode *MS,
@@ -54197,6 +54197,14 @@ static SDValue reduceMaskedStoreToScalarStore(MaskedStoreSDNode *MS,
   SDValue Extract =
       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Value, VecIndex);
 
+  if (MS->isTruncatingStore()) {
+    if (EltVT.isFloatingPoint())
+      return SDValue();
+
+    Extract = DAG.getNode(ISD::TRUNCATE, DL,
+                          MS->getMemoryVT().getVectorElementType(), Extract);
+  }
+
   // Store that element at the appropriate offset from the base pointer.
   return DAG.getStore(MS->getChain(), DL, Extract, Addr,
                       MS->getPointerInfo().getWithOffset(Offset),

diff  --git a/llvm/test/CodeGen/X86/pr179489.ll b/llvm/test/CodeGen/X86/pr179489.ll
new file mode 100644
index 0000000000000..e59261e00719f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr179489.ll
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx10.2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx10.2 | FileCheck %s --check-prefix=X64
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
+declare void @llvm.masked.store.v8i8.p1(<8 x i8>, ptr addrspace(1) captures(none), <8 x i1>) #0
+
+define void @foo(<8 x i16> %arg, ptr addrspace(1) %add.ptr) {
+; X86-LABEL: foo:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    vmovw %xmm0, %ecx
+; X86-NEXT:    movb %ch, (%eax)
+; X86-NEXT:    retl
+;
+; X64-LABEL: foo:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    vmovw %xmm0, %eax
+; X64-NEXT:    movb %ah, (%rdi)
+; X64-NEXT:    retq
+entry:
+  %i3 = shufflevector <8 x i16> %arg, <8 x i16> <i16 poison, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %i4 = lshr <8 x i16> %i3, splat (i16 8)
+  %i5 = trunc <8 x i16> %i4 to <8 x i8>
+  call void @llvm.masked.store.v8i8.p1(<8 x i8> %i5, ptr addrspace(1) %add.ptr, <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>)
+  ret void
+}
+
+define void @bar(<8 x i64> %arg, ptr addrspace(1) %add.ptr) {
+; X86-LABEL: bar:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    vpbroadcastd {{.*#+}} zmm1 = [257,257,257,257,257,257,257,257,257,257,257,257,257,257,257,257]
+; X86-NEXT:    movb $2, %al
+; X86-NEXT:    kmovd %eax, %k1
+; X86-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    vpsrlq $16, %zmm1, %zmm0
+; X86-NEXT:    vpmovqb %zmm0, (%eax) {%k1}
+; X86-NEXT:    vzeroupper
+; X86-NEXT:    retl
+;
+; X64-LABEL: bar:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    vpextrq $1, %xmm0, %rax
+; X64-NEXT:    shrl $16, %eax
+; X64-NEXT:    movb %al, 1(%rdi)
+; X64-NEXT:    vzeroupper
+; X64-NEXT:    retq
+entry:
+  %i3 = shufflevector <8 x i64> %arg, <8 x i64> <i64 257, i64 poison, i64 257, i64 257, i64 257, i64 257, i64 257, i64 257>, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %i4 = lshr <8 x i64> %i3, splat (i64 16)
+  %i5 = trunc <8 x i64> %i4 to <8 x i8>
+  call void @llvm.masked.store.v8i8.p1(<8 x i8> %i5, ptr addrspace(1) %add.ptr, <8 x i1> <i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>)
+  ret void
+}
+
+attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }