[llvm] [RISCV] Improve loop by extract reduction instruction (PR #179215)

[via llvm-commits]

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@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; loop-reduce-motion-test.ll
+; RUN: opt -passes=loop-reduce-motion -S < %s | FileCheck %s
+
+define i32 @pixel_asd8(ptr %pix1, i64 %stride1, ptr %pix2, i64 %stride2, i32 %height) {
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Anjian-Wen wrote:

Thanks for your reviews, I will add more tests about multi block/multi exit loops. 

Yes, I agree, At first, I try to place this pass after `VectorCombine` as a general pass.
However, considering that general optimizations might have a broader impact, I decided to debug and test it under the RISC-V architecture first. I will try to change it back to general pass
> I don't think here is anything RISCV specific about this pattch. I think it would be preferable if it would just run after the vectorizers generally?



https://github.com/llvm/llvm-project/pull/179215