[llvm] [ARM] Use REG_SEQUENCE instead of SUBREG_TO_REG for crypto patterns. NFCI. (PR #179910)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-arm

Author: Jay Foad (jayfoad)

<details>
<summary>Changes</summary>

This removes the only uses of SUBREG_TO_REG in the ARM backend.


---
Full diff: https://github.com/llvm/llvm-project/pull/179910.diff


1 Files Affected:

- (modified) llvm/lib/Target/ARM/ARMInstrNEON.td (+16-8) 


``````````diff
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index e2450490c83b8..8e8ef64991e14 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -7403,26 +7403,34 @@ def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
 let Predicates = [HasNEON] in {
 def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)),
           (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
-              (SHA1H (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
-                                    ssub_0)),
+              (SHA1H (REG_SEQUENCE QPR, (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)), ssub_0,
+                                        (i32 (IMPLICIT_DEF)), ssub_1,
+                                        (i32 (IMPLICIT_DEF)), ssub_2,
+                                        (i32 (IMPLICIT_DEF)), ssub_3)),
               ssub_0)), GPR)>;
 
 def : Pat<(v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
           (SHA1C v4i32:$hash_abcd,
-                 (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
-                                ssub_0),
+                 (REG_SEQUENCE QPR, (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0,
+                                    (i32 (IMPLICIT_DEF)), ssub_1,
+                                    (i32 (IMPLICIT_DEF)), ssub_2,
+                                    (i32 (IMPLICIT_DEF)), ssub_3),
                  v4i32:$wk)>;
 
 def : Pat<(v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
           (SHA1M v4i32:$hash_abcd,
-                 (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
-                                ssub_0),
+                 (REG_SEQUENCE QPR, (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0,
+                                    (i32 (IMPLICIT_DEF)), ssub_1,
+                                    (i32 (IMPLICIT_DEF)), ssub_2,
+                                    (i32 (IMPLICIT_DEF)), ssub_3),
                  v4i32:$wk)>;
 
 def : Pat<(v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
           (SHA1P v4i32:$hash_abcd,
-                 (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
-                                ssub_0),
+                 (REG_SEQUENCE QPR, (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0,
+                                    (i32 (IMPLICIT_DEF)), ssub_1,
+                                    (i32 (IMPLICIT_DEF)), ssub_2,
+                                    (i32 (IMPLICIT_DEF)), ssub_3),
                  v4i32:$wk)>;
 }
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/179910