[llvm] [RISCV] Remove redundant vand.vi with fpto*i to i1 (PR #179876)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 4 23:48:00 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Luke Lau (lukel97)
<details>
<summary>Changes</summary>
If the source of an fpto*i doesn't fit in the destination type, the result is poison. For i1 destinations, this means the result needs to be 0 or 1/-1, so we can just compare the result to 0 directly instead of truncating.
The VP lowering for fpto*i already does this.
---
Patch is 29.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/179876.diff
3 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll (+12-28)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll (+30-88)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d17911994e891..b4b06117d2271 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8186,6 +8186,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return DAG.getMergeValues({Res, FP2Int.getValue(1)}, DL);
}
SDValue FP2Int = DAG.getNode(Op.getOpcode(), DL, IVecVT, Src);
+ if (EltSize == 1)
+ // The integer should be 0 or 1/-1, so compare the integer result to 0.
+ return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, IVecVT), FP2Int,
+ ISD::SETNE);
return DAG.getNode(ISD::TRUNCATE, DL, VT, FP2Int);
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
index 9be93d5209121..ea791a155d3d6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
@@ -37,8 +37,7 @@ define <2 x i1> @fp2si_v2f32_v2i1(<2 x float> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vand.vi v8, v9, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%z = fptosi <2 x float> %x to <2 x i1>
ret <2 x i1> %z
@@ -71,8 +70,7 @@ define <2 x i1> @fp2ui_v2f32_v2i1(<2 x float> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vand.vi v8, v9, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%z = fptoui <2 x float> %x to <2 x i1>
ret <2 x i1> %z
@@ -111,8 +109,7 @@ define <3 x i1> @fp2si_v3f32_v3i1(<3 x float> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vand.vi v8, v9, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%z = fptosi <3 x float> %x to <3 x i1>
ret <3 x i1> %z
@@ -309,8 +306,7 @@ define <3 x i1> @fp2ui_v3f32_v3i1(<3 x float> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vand.vi v8, v9, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%z = fptoui <3 x float> %x to <3 x i1>
ret <3 x i1> %z
@@ -349,8 +345,7 @@ define <8 x i1> @fp2si_v8f32_v8i1(<8 x float> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
-; CHECK-NEXT: vand.vi v8, v10, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: ret
%z = fptosi <8 x float> %x to <8 x i1>
ret <8 x i1> %z
@@ -361,8 +356,7 @@ define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
-; CHECK-NEXT: vand.vi v8, v10, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: ret
%z = fptoui <8 x float> %x to <8 x i1>
ret <8 x i1> %z
@@ -462,7 +456,6 @@ define <2 x i1> @fp2si_v2bf16_v2i1(<2 x bfloat> %x) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%z = fptosi <2 x bfloat> %x to <2 x i1>
@@ -475,7 +468,6 @@ define <2 x i1> @fp2ui_v2bf16_v2i1(<2 x bfloat> %x) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%z = fptoui <2 x bfloat> %x to <2 x i1>
@@ -519,8 +511,7 @@ define <2 x i1> @fp2si_v2f16_v2i1(<2 x half> %x) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
-; ZVFH-NEXT: vand.vi v8, v9, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: fp2si_v2f16_v2i1:
@@ -528,7 +519,6 @@ define <2 x i1> @fp2si_v2f16_v2i1(<2 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%z = fptosi <2 x half> %x to <2 x i1>
@@ -540,8 +530,7 @@ define <2 x i1> @fp2ui_v2f16_v2i1(<2 x half> %x) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; ZVFH-NEXT: vand.vi v8, v9, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: fp2ui_v2f16_v2i1:
@@ -549,7 +538,6 @@ define <2 x i1> @fp2ui_v2f16_v2i1(<2 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%z = fptoui <2 x half> %x to <2 x i1>
@@ -597,8 +585,7 @@ define <2 x i1> @fp2si_v2f64_v2i1(<2 x double> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vand.vi v8, v9, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%z = fptosi <2 x double> %x to <2 x i1>
ret <2 x i1> %z
@@ -609,8 +596,7 @@ define <2 x i1> @fp2ui_v2f64_v2i1(<2 x double> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vand.vi v8, v9, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%z = fptoui <2 x double> %x to <2 x i1>
ret <2 x i1> %z
@@ -657,8 +643,7 @@ define <8 x i1> @fp2si_v8f64_v8i1(<8 x double> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
-; CHECK-NEXT: vand.vi v8, v12, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: ret
%z = fptosi <8 x double> %x to <8 x i1>
ret <8 x i1> %z
@@ -669,8 +654,7 @@ define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
-; CHECK-NEXT: vand.vi v8, v12, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: ret
%z = fptoui <8 x double> %x to <8 x i1>
ret <8 x i1> %z
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
index 111fa368ac155..45a6a4d95be02 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
@@ -18,7 +18,6 @@ define <vscale x 1 x i1> @vfptosi_nxv1bf16_nxv1i1(<vscale x 1 x bfloat> %va) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i1>
@@ -57,7 +56,6 @@ define <vscale x 1 x i1> @vfptoui_nxv1bf16_nxv1i1(<vscale x 1 x bfloat> %va) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i1>
@@ -166,7 +164,6 @@ define <vscale x 2 x i1> @vfptosi_nxv2bf16_nxv2i1(<vscale x 2 x bfloat> %va) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i1>
@@ -179,7 +176,6 @@ define <vscale x 2 x i1> @vfptoui_nxv2bf16_nxv2i1(<vscale x 2 x bfloat> %va) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i1>
@@ -288,7 +284,6 @@ define <vscale x 4 x i1> @vfptosi_nxv4bf16_nxv4i1(<vscale x 4 x bfloat> %va) {
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x bfloat> %va to <vscale x 4 x i1>
@@ -301,7 +296,6 @@ define <vscale x 4 x i1> @vfptoui_nxv4bf16_nxv4i1(<vscale x 4 x bfloat> %va) {
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x bfloat> %va to <vscale x 4 x i1>
@@ -410,7 +404,6 @@ define <vscale x 8 x i1> @vfptosi_nxv8bf16_nxv8i1(<vscale x 8 x bfloat> %va) {
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x bfloat> %va to <vscale x 8 x i1>
@@ -423,7 +416,6 @@ define <vscale x 8 x i1> @vfptoui_nxv8bf16_nxv8i1(<vscale x 8 x bfloat> %va) {
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x bfloat> %va to <vscale x 8 x i1>
@@ -532,7 +524,6 @@ define <vscale x 16 x i1> @vfptosi_nxv16bf16_nxv16i1(<vscale x 16 x bfloat> %va)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 16 x bfloat> %va to <vscale x 16 x i1>
@@ -545,7 +536,6 @@ define <vscale x 16 x i1> @vfptoui_nxv16bf16_nxv16i1(<vscale x 16 x bfloat> %va)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16
-; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 16 x bfloat> %va to <vscale x 16 x i1>
@@ -634,8 +624,6 @@ define <vscale x 32 x i1> @vfptosi_nxv32bf16_nxv32i1(<vscale x 32 x bfloat> %va)
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v24
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vand.vi v12, v12, 1
; CHECK-NEXT: vmsne.vi v16, v8, 0
; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
@@ -655,8 +643,6 @@ define <vscale x 32 x i1> @vfptoui_nxv32bf16_nxv32i1(<vscale x 32 x bfloat> %va)
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v24
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vand.vi v12, v12, 1
; CHECK-NEXT: vmsne.vi v16, v8, 0
; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
@@ -733,8 +719,7 @@ define <vscale x 1 x i1> @vfptosi_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
-; ZVFH-NEXT: vand.vi v8, v9, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptosi_nxv1f16_nxv1i1:
@@ -742,7 +727,6 @@ define <vscale x 1 x i1> @vfptosi_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%evec = fptosi <vscale x 1 x half> %va to <vscale x 1 x i1>
@@ -794,8 +778,7 @@ define <vscale x 1 x i1> @vfptoui_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; ZVFH-NEXT: vand.vi v8, v9, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptoui_nxv1f16_nxv1i1:
@@ -803,7 +786,6 @@ define <vscale x 1 x i1> @vfptoui_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%evec = fptoui <vscale x 1 x half> %va to <vscale x 1 x i1>
@@ -951,8 +933,7 @@ define <vscale x 2 x i1> @vfptosi_nxv2f16_nxv2i1(<vscale x 2 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
-; ZVFH-NEXT: vand.vi v8, v9, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptosi_nxv2f16_nxv2i1:
@@ -960,7 +941,6 @@ define <vscale x 2 x i1> @vfptosi_nxv2f16_nxv2i1(<vscale x 2 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%evec = fptosi <vscale x 2 x half> %va to <vscale x 2 x i1>
@@ -972,8 +952,7 @@ define <vscale x 2 x i1> @vfptoui_nxv2f16_nxv2i1(<vscale x 2 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; ZVFH-NEXT: vand.vi v8, v9, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptoui_nxv2f16_nxv2i1:
@@ -981,7 +960,6 @@ define <vscale x 2 x i1> @vfptoui_nxv2f16_nxv2i1(<vscale x 2 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%evec = fptoui <vscale x 2 x half> %va to <vscale x 2 x i1>
@@ -1129,8 +1107,7 @@ define <vscale x 4 x i1> @vfptosi_nxv4f16_nxv4i1(<vscale x 4 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
-; ZVFH-NEXT: vand.vi v8, v9, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptosi_nxv4f16_nxv4i1:
@@ -1138,7 +1115,6 @@ define <vscale x 4 x i1> @vfptosi_nxv4f16_nxv4i1(<vscale x 4 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v10
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%evec = fptosi <vscale x 4 x half> %va to <vscale x 4 x i1>
@@ -1150,8 +1126,7 @@ define <vscale x 4 x i1> @vfptoui_nxv4f16_nxv4i1(<vscale x 4 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; ZVFH-NEXT: vand.vi v8, v9, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptoui_nxv4f16_nxv4i1:
@@ -1159,7 +1134,6 @@ define <vscale x 4 x i1> @vfptoui_nxv4f16_nxv4i1(<vscale x 4 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v10
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%evec = fptoui <vscale x 4 x half> %va to <vscale x 4 x i1>
@@ -1307,8 +1281,7 @@ define <vscale x 8 x i1> @vfptosi_nxv8f16_nxv8i1(<vscale x 8 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; ZVFH-NEXT: vfncvt.rtz.x.f.w v10, v8
-; ZVFH-NEXT: vand.vi v8, v10, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v10, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptosi_nxv8f16_nxv8i1:
@@ -1316,7 +1289,6 @@ define <vscale x 8 x i1> @vfptosi_nxv8f16_nxv8i1(<vscale x 8 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v12
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%evec = fptosi <vscale x 8 x half> %va to <vscale x 8 x i1>
@@ -1328,8 +1300,7 @@ define <vscale x 8 x i1> @vfptoui_nxv8f16_nxv8i1(<vscale x 8 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v10, v8
-; ZVFH-NEXT: vand.vi v8, v10, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v10, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptoui_nxv8f16_nxv8i1:
@@ -1337,7 +1308,6 @@ define <vscale x 8 x i1> @vfptoui_nxv8f16_nxv8i1(<vscale x 8 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v12
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%evec = fptoui <vscale x 8 x half> %va to <vscale x 8 x i1>
@@ -1485,8 +1455,7 @@ define <vscale x 16 x i1> @vfptosi_nxv16f16_nxv16i1(<vscale x 16 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVFH-NEXT: vfncvt.rtz.x.f.w v12, v8
-; ZVFH-NEXT: vand.vi v8, v12, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v12, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptosi_nxv16f16_nxv16i1:
@@ -1494,7 +1463,6 @@ define <vscale x 16 x i1> @vfptosi_nxv16f16_nxv16i1(<vscale x 16 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v16
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%evec = fptosi <vscale x 16 x half> %va to <vscale x 16 x i1>
@@ -1506,8 +1474,7 @@ define <vscale x 16 x i1> @vfptoui_nxv16f16_nxv16i1(<vscale x 16 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v12, v8
-; ZVFH-NEXT: vand.vi v8, v12, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v12, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptoui_nxv16f16_nxv16i1:
@@ -1515,7 +1482,6 @@ define <vscale x 16 x i1> @vfptoui_nxv16f16_nxv16i1(<vscale x 16 x half> %va) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v16
-; ZVFHMIN-NEXT: vand.vi v8, v8, 1
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%evec = fptoui <vscale x 16 x half> %va to <vscale x 16 x i1>
@@ -1639,8 +1605,7 @@ define <vscale x 32 x i1> @vfptosi_nxv32f16_nxv32i1(<vscale x 32 x half> %va) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZVFH-NEXT: vfncvt.rtz.x.f.w v16, v8
-; ZVFH-NEXT: vand.vi v8, v16, 1
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vmsne.vi v0, v16, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptosi_nxv32f16_nxv32i1:
@@ -1652,8 +1617,6 @@ define <vscale x 32 x i1> @vfptosi_nxv32f16_nxv32i1(<vscale x 32 x h...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/179876
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