[llvm] 2ca54b4 - [MachinePipeliner] Remove isLoopCarriedDep calls in computeStart (#174393)
via llvm-commits
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Wed Feb 4 22:05:53 PST 2026
Author: Ryotaro Kasuga
Date: 2026-02-05T06:05:48Z
New Revision: 2ca54b41a45e5292d2e56e933da905e86e2480b8
URL: https://github.com/llvm/llvm-project/commit/2ca54b41a45e5292d2e56e933da905e86e2480b8
DIFF: https://github.com/llvm/llvm-project/commit/2ca54b41a45e5292d2e56e933da905e86e2480b8.diff
LOG: [MachinePipeliner] Remove isLoopCarriedDep calls in computeStart (#174393)
When computing the viable cycles for scheduling an instruction,
`computeStart` used to include special-case logic to handle loop-carried
dependencies. This special handling was necessary because loop-carried
dependencies were represented by reversed forward-direction edges in the
DAG. Now that we have the DDG, which explicitly models loop-carried
dependencies, this special handling is no longer required. As a first
step towards completely removing `isLoopCarriedDep`, this patch
eliminates the special-case logic from `computeStart` and some related
functions.
Split off from https://github.com/llvm/llvm-project/pull/135148
Added:
Modified:
llvm/include/llvm/CodeGen/MachinePipeliner.h
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h
index 6326fd4862d92..cf7901ad697de 100644
--- a/llvm/include/llvm/CodeGen/MachinePipeliner.h
+++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h
@@ -776,16 +776,6 @@ class SMSchedule {
/// Return the last cycle in the finalized schedule.
int getFinalCycle() const { return FirstCycle + InitiationInterval - 1; }
- /// Return the cycle of the earliest scheduled instruction in the dependence
- /// chain.
- int earliestCycleInChain(const SwingSchedulerDDGEdge &Dep,
- const SwingSchedulerDDG *DDG);
-
- /// Return the cycle of the latest scheduled instruction in the dependence
- /// chain.
- int latestCycleInChain(const SwingSchedulerDDGEdge &Dep,
- const SwingSchedulerDDG *DDG);
-
void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int II,
SwingSchedulerDAG *DAG);
bool insert(SUnit *SU, int StartCycle, int EndCycle, int II);
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 5e6e1cbfdd7ea..43bb19bf4f181 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -3318,54 +3318,6 @@ bool SMSchedule::insert(SUnit *SU, int StartCycle, int EndCycle, int II) {
return false;
}
-// Return the cycle of the earliest scheduled instruction in the chain.
-int SMSchedule::earliestCycleInChain(const SwingSchedulerDDGEdge &Dep,
- const SwingSchedulerDDG *DDG) {
- SmallPtrSet<SUnit *, 8> Visited;
- SmallVector<SwingSchedulerDDGEdge, 8> Worklist;
- Worklist.push_back(Dep);
- int EarlyCycle = INT_MAX;
- while (!Worklist.empty()) {
- const SwingSchedulerDDGEdge &Cur = Worklist.pop_back_val();
- SUnit *PrevSU = Cur.getSrc();
- if (Visited.count(PrevSU))
- continue;
- std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(PrevSU);
- if (it == InstrToCycle.end())
- continue;
- EarlyCycle = std::min(EarlyCycle, it->second);
- for (const auto &IE : DDG->getInEdges(PrevSU))
- if (IE.isOrderDep() || IE.isOutputDep())
- Worklist.push_back(IE);
- Visited.insert(PrevSU);
- }
- return EarlyCycle;
-}
-
-// Return the cycle of the latest scheduled instruction in the chain.
-int SMSchedule::latestCycleInChain(const SwingSchedulerDDGEdge &Dep,
- const SwingSchedulerDDG *DDG) {
- SmallPtrSet<SUnit *, 8> Visited;
- SmallVector<SwingSchedulerDDGEdge, 8> Worklist;
- Worklist.push_back(Dep);
- int LateCycle = INT_MIN;
- while (!Worklist.empty()) {
- const SwingSchedulerDDGEdge &Cur = Worklist.pop_back_val();
- SUnit *SuccSU = Cur.getDst();
- if (Visited.count(SuccSU) || SuccSU->isBoundaryNode())
- continue;
- std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SuccSU);
- if (it == InstrToCycle.end())
- continue;
- LateCycle = std::max(LateCycle, it->second);
- for (const auto &OE : DDG->getOutEdges(SuccSU))
- if (OE.isOrderDep() || OE.isOutputDep())
- Worklist.push_back(OE);
- Visited.insert(SuccSU);
- }
- return LateCycle;
-}
-
/// If an instruction has a use that spans multiple iterations, then
/// return true. These instructions are characterized by having a back-ege
/// to a Phi, which contains a reference to another Phi.
@@ -3391,12 +3343,6 @@ void SMSchedule::computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart,
for (SUnit *I : getInstructions(cycle)) {
for (const auto &IE : DDG->getInEdges(SU)) {
if (IE.getSrc() == I) {
- // FIXME: Add reverse edge to `DDG` instead of calling
- // `isLoopCarriedDep`
- if (DAG->isLoopCarriedDep(IE)) {
- int End = earliestCycleInChain(IE, DDG) + (II - 1);
- *MinLateStart = std::min(*MinLateStart, End);
- }
int EarlyStart = cycle + IE.getLatency() - IE.getDistance() * II;
*MaxEarlyStart = std::max(*MaxEarlyStart, EarlyStart);
}
@@ -3404,12 +3350,6 @@ void SMSchedule::computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart,
for (const auto &OE : DDG->getOutEdges(SU)) {
if (OE.getDst() == I) {
- // FIXME: Add reverse edge to `DDG` instead of calling
- // `isLoopCarriedDep`
- if (DAG->isLoopCarriedDep(OE)) {
- int Start = latestCycleInChain(OE, DDG) + 1 - II;
- *MaxEarlyStart = std::max(*MaxEarlyStart, Start);
- }
int LateStart = cycle - OE.getLatency() + OE.getDistance() * II;
*MinLateStart = std::min(*MinLateStart, LateStart);
}
diff --git a/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir b/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir
index 120ea5dc3ef16..3a984f6488700 100644
--- a/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir
+++ b/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir
@@ -6,9 +6,9 @@
# CHECK: {{^ *}}Try to schedule with 47
# CHECK: {{^ *}}Inst (11) %48:fpr128 = LDRQui %35:gpr64sp, 0 :: (load (s128) from %ir.lsr.iv63, align 4, !tbaa !0)
# CHECK-EMPTY:
-# CHECK-NEXT: {{^ *}}es: ffffffe9 ls: ffffffe9
-# CHECK-NEXT: {{^ *}}Trying to insert node between -23 and -23 II: 47
-# CHECK-NEXT: {{^ *}}failed to insert at cycle -23 %48:fpr128 = LDRQui %35:gpr64sp, 0 :: (load (s128) from %ir.lsr.iv63, align 4, !tbaa !0)
+# CHECK-NEXT: {{^ *}}es: ffffffe8 ls: ffffffe9
+# CHECK-NEXT: {{^ *}}Trying to insert node between -24 and -23 II: 47
+# CHECK-NEXT: {{^ *}}insert at cycle -24 %48:fpr128 = LDRQui %35:gpr64sp, 0 :: (load (s128) from %ir.lsr.iv63, align 4, !tbaa !0)
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
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