[llvm] Removed incorrect "DS Store drain" check. (PR #179818)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: None (hidekisaito)

<details>
<summary>Changes</summary>

Checking for S_BARRIER only does not imply prior DS Stores getting drained.

---
Full diff: https://github.com/llvm/llvm-project/pull/179818.diff


1 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp (+2-6) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 9a2a7b4923881..a6114496985e5 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -3246,14 +3246,10 @@ SIInsertWaitcnts::getPreheaderFlushFlags(MachineLoop *ML,
         HasVMemLoad |= MI.mayLoad();
         HasVMemStore |= MI.mayStore();
       }
+      // TODO: Can we relax SeenDSStoreInLoop? There may be cases where
+      // these DS stores are drained prior to the end of MBB (or loop).
       if (mayStoreIncrementingDSCNT(MI))
         SeenDSStoreInCurrMBB = true;
-      // Stores postdominated by a barrier will have a wait at the barrier
-      // and thus no need to be waited at the loop header. Barrier found
-      // later in the same MBB during in-order traversal is used here as a
-      // cheaper alternative to postdomination check.
-      if (MI.getOpcode() == AMDGPU::S_BARRIER)
-        SeenDSStoreInCurrMBB = false;
       for (const MachineOperand &Op : MI.all_uses()) {
         if (Op.isDebug() || !TRI->isVectorRegister(*MRI, Op.getReg()))
           continue;

``````````

</details>


https://github.com/llvm/llvm-project/pull/179818