[llvm] [AMDGPU] fix eliminateFrameIndex to use SGPR frame index (PR #178991)
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Wed Feb 4 10:18:55 PST 2026
https://github.com/hjagasiaAMD updated https://github.com/llvm/llvm-project/pull/178991
>From ff1a452313414865ea5db7d0d59b790c06b184dc Mon Sep 17 00:00:00 2001
From: hjagasiaAMD <harsha.jagasia at amd.com>
Date: Fri, 30 Jan 2026 17:10:15 -0600
Subject: [PATCH 1/3] [AMDGPU] fix eliminateFrameIndex to use SGPR frame index
---
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 --
.../AMDGPU/eliminate-frame-index-select.mir | 35 +++++++++++++++++++
2 files changed, 35 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 96c2f6530fe4c..3df9a78a391bc 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3257,8 +3257,6 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
if (!IsSALU)
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg)
.addReg(TmpResultReg, RegState::Kill);
- else
- ResultReg = TmpResultReg;
// If there were truly no free SGPRs, we need to undo everything.
if (!TmpScaledReg.isValid()) {
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg)
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
new file mode 100644
index 0000000000000..8ce4428a3f20b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
@@ -0,0 +1,35 @@
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1030 -run-pass prologepilog -o - %s | FileCheck %s
+# CHECK: $sgpr5 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
+# CHECK: renamable $sgpr4 = S_CSELECT_B32 0, killed $sgpr5, implicit $scc
+--- |
+ %struct.wobble = type { %struct.quux }
+ %struct.quux = type { float, float, float }
+ define void @wobble() {
+ %alloca = alloca %struct.wobble, align 4, addrspace(5)
+ ret void
+ }
+...
+---
+name: wobble
+tracksRegLiveness: true
+stack:
+ - { id: 0, name: alloca, offset: 0, size: 12}
+machineFunctionInfo:
+ scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
+ frameOffsetReg: '$sgpr33'
+ stackPtrOffsetReg: '$sgpr32'
+body: |
+ bb.0:
+ renamable $vgpr41 = V_MOV_B32_e32 0, implicit $exec
+ renamable $sgpr4 = S_MOV_B32 0
+ renamable $sgpr54 = S_ADD_I32 %stack.0.alloca, 4, implicit-def dead $scc
+ bb.1:
+ liveins: $sgpr4, $sgpr54:0x000000000000000F
+ S_CMP_EQ_U32 killed renamable $sgpr4, 0, implicit-def $scc
+ renamable $sgpr4 = S_CSELECT_B32 0, %stack.0.alloca, implicit $scc
+ renamable $sgpr5 = S_CSELECT_B32 4, renamable $sgpr54, implicit $scc
+ S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
+ S_BRANCH %bb.2
+ bb.2:
+ SI_RETURN
+...
>From adffe15966b7d5baccdc5403b1df3102e1c91ce6 Mon Sep 17 00:00:00 2001
From: hjagasiaAMD <harsha.jagasia at amd.com>
Date: Mon, 2 Feb 2026 16:30:51 -0600
Subject: [PATCH 2/3] [AMDGPU] Fix lit tests
---
.../AMDGPU/eliminate-frame-index-select.ll | 35 +++++++++++++++++++
.../AMDGPU/eliminate-frame-index-select.mir | 28 +++++++--------
2 files changed, 47 insertions(+), 16 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
new file mode 100644
index 0000000000000..f246ba57410e2
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
@@ -0,0 +1,35 @@
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s
+; CHECK-LABEL: .LBB0_1:
+; CHECK: v_lshrrev_b32_e64 [[V:v[0-9]+]], 5, s33
+; CHECK: v_add_nc_u32_e32 [[V]], 12, [[V]]
+; CHECK: v_readfirstlane_b32 [[S:s[0-9]+]], [[V]]
+; CHECK: s_cselect_b32 {{s[0-9]+}}, 0, [[S]]
+
+%struct.wobble = type { %struct.quux }
+%struct.quux = type { float, float, float }
+
+declare %struct.wobble @foo(%struct.quux)
+
+define void @wobble() #0 {
+bb:
+ %alloca = alloca %struct.wobble, align 4, addrspace(5)
+ br label %bb1
+
+bb1: ; preds = %bb1, %bb
+ %phi = phi i32 [ 0, %bb ], [ 1, %bb1 ]
+ store i32 0, ptr addrspacecast (ptr addrspace(5) null to ptr), align 4
+ %getelementptr = getelementptr i8, ptr addrspace(5) %alloca, i32 4
+ %icmp = icmp eq i32 %phi, 0
+ %load = load float, ptr addrspace(5) null, align 2147483648
+ %load2 = load float, ptr addrspace(5) %alloca, align 4
+ %select = select i1 %icmp, float %load, float %load2
+ %insertvalue = insertvalue %struct.quux zeroinitializer, float %select, 0
+ %load3 = load float, ptr addrspace(5) inttoptr (i32 4 to ptr addrspace(5)), align 4
+ %load4 = load float, ptr addrspace(5) %getelementptr, align 4
+ %select5 = select i1 %icmp, float %load3, float %load4
+ %insertvalue6 = insertvalue %struct.quux %insertvalue, float %select5, 1
+ %call = call %struct.wobble @foo(%struct.quux %insertvalue6)
+ br label %bb1
+}
+
+attributes #0 = { "target-cpu"="gfx1030" }
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
index 8ce4428a3f20b..cbd6149b97d98 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
@@ -1,34 +1,30 @@
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1030 -run-pass prologepilog -o - %s | FileCheck %s
-# CHECK: $sgpr5 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
-# CHECK: renamable $sgpr4 = S_CSELECT_B32 0, killed $sgpr5, implicit $scc
---- |
- %struct.wobble = type { %struct.quux }
- %struct.quux = type { float, float, float }
- define void @wobble() {
- %alloca = alloca %struct.wobble, align 4, addrspace(5)
- ret void
- }
-...
+# CHECK: bb.1:
+# CHECK: [[V1:\$vgpr[0-9]+]] = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec
+# CHECK: [[R1:\$sgpr[0-9]+]] = V_READFIRSTLANE_B32 [[V1]], implicit $exec
+# CHECK: S_CSELECT_B32 0, killed [[R1]], implicit $scc
+# CHECK: [[V2:\$vgpr[0-9]+]] = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec
+# CHECK: [[R2:\$sgpr[0-9]+]] = V_READFIRSTLANE_B32 [[V2]], implicit $exec
+# CHECK: S_CSELECT_B32 killed [[R2]], 0, implicit $scc
---
-name: wobble
+name: test
tracksRegLiveness: true
stack:
- - { id: 0, name: alloca, offset: 0, size: 12}
+ - { id: 0, size: 12}
machineFunctionInfo:
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
frameOffsetReg: '$sgpr33'
stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
- renamable $vgpr41 = V_MOV_B32_e32 0, implicit $exec
renamable $sgpr4 = S_MOV_B32 0
- renamable $sgpr54 = S_ADD_I32 %stack.0.alloca, 4, implicit-def dead $scc
+ renamable $sgpr54 = S_ADD_I32 %stack.0, 4, implicit-def dead $scc
bb.1:
liveins: $sgpr4, $sgpr54:0x000000000000000F
S_CMP_EQ_U32 killed renamable $sgpr4, 0, implicit-def $scc
- renamable $sgpr4 = S_CSELECT_B32 0, %stack.0.alloca, implicit $scc
+ renamable $sgpr4 = S_CSELECT_B32 0, %stack.0, implicit $scc
+ renamable $sgpr6 = S_CSELECT_B32 %stack.0, 0, implicit $scc
renamable $sgpr5 = S_CSELECT_B32 4, renamable $sgpr54, implicit $scc
- S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
S_BRANCH %bb.2
bb.2:
SI_RETURN
>From 20bd5d9d4e96806c37605f130af7286ee878a992 Mon Sep 17 00:00:00 2001
From: hjagasiaAMD <harsha.jagasia at amd.com>
Date: Wed, 4 Feb 2026 12:18:46 -0600
Subject: [PATCH 3/3] Update
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
index f246ba57410e2..d1b89a40d738b 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck %s
; CHECK-LABEL: .LBB0_1:
; CHECK: v_lshrrev_b32_e64 [[V:v[0-9]+]], 5, s33
; CHECK: v_add_nc_u32_e32 [[V]], 12, [[V]]
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