[llvm] 6d96ae6 - [RISCV] Add tied destination constraint to CustomSiFiveVMACC. (#179567)

[via llvm-commits]

Author: Craig Topper
Date: 2026-02-04T17:58:07Z
New Revision: 6d96ae6aa86feaece76f14d8b52d1d2d5d641914

URL: https://github.com/llvm/llvm-project/commit/6d96ae6aa86feaece76f14d8b52d1d2d5d641914
DIFF: https://github.com/llvm/llvm-project/commit/6d96ae6aa86feaece76f14d8b52d1d2d5d641914.diff

LOG: [RISCV] Add tied destination constraint to CustomSiFiveVMACC. (#179567)

As the name suggess, these are multiply-accumulate instructions and
thus they have 3 sources.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index 5723f3ac0c02f..6051cf1aa5abf 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -182,7 +182,7 @@ class SiFiveVMACCScheds<string name> {
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVV<funct6, opv, (outs VR:$vd), (ins VR:$vs1, VR:$vs2), opcodestr,
+    : RVInstVV<funct6, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs1, VR:$vs2), opcodestr,
                "$vd, $vs1, $vs2">,
       SchedTernaryMC<SiFiveVMACCScheds<NAME>.write,
                      SiFiveVMACCScheds<NAME>.read,
@@ -192,6 +192,7 @@ class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr>
 
   let Inst{6-0} = OPC_CUSTOM_2.Value;
 
+  let Constraints = "$vd = $vd_wb";
   let RVVConstraint = NoConstraint;
   let ElementsDependOn = EltDepsVLMask;
   let ReadsPastVL = true;